Catalyzr™ Security Risk Assessment (SW)
Catalyzr leverage a tool-based approach to guide the correct usage of crypto-APIs, then developers can benefit from the expertise and experience of cryptographic specialists, ensuring more robust and secure implementations of cryptographic functionality within their applications
By Secure-IC SAS
CIC FPGA IP Core
The CIC FPGA IP core offers computationally efficient cores for extracting baseband signals.
By Altera
CoaXPress Device IP Core
IP Core for CoaXPress camera applications with speed support from 1 Gbps up to 100 Gbps.
By Sensor to Image GmbH
Comet A65 SOM
The Comet A65 SOM is a high-performance System-On-Module powered by Altera’s largest Agilex™ 5 SoC FPGA, designed for demanding industrial edge applications.
By Terasic Inc.
Comet A65 SOM
The Comet A65 SOM is Terasic’s production-ready System-on-Module built on Altera’s largest Agilex® 5 SoC FPGA (656K LEs). With integrated HPS/ARM, 12GB LPDDR4, and high-speed expansion connectors, it delivers a powerful, scalable platform for industrial edge applications — from robotics to medical imaging — all with a free Altera® Quartus® Pro Edition license included.
By Terasic Inc.
Consulting for electrical characteristics of printed circuit boards
For signal transmission and noise problems in the development of electronic devices, especially those using Altera FPGA-based boards, we utilize our proprietary electronic measuring instruments and simulation software to identify issues and propose effective improvements.
By RITA Electronics, Ltd.
CPRI FPGA IP
Altera CPRI FPGA IP delivers a high-performance, standards-compliant implementation of the CPRI Specification V7.0, enabling reliable, high-speed communication between Radio Equipment Controllers (RECs) and Remote Radio Equipment (REs). Fully configurable as either REC or RE, the IP simplifies integration in remote radio network applications and accelerates deployment of robust, low-latency fronthaul links.
By Altera
CSENT-Rx: SENT/SAE J2716 Receiver
The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and supports both synchronous and asynchronous sensors. It can be used for receiving data from one or multiple sensors using a single SENT line. The CSENT-RX provides access to its control, status, and data registers via a 32-bit APB, or AXI4-Lite bus interface. The core provides a glitch filter on the serial data input and has data mapping functionality on received data to offload the connected host from data formatting. The received data are accessible via the register interface. The core is also capable of generating trigger pulses requesting synchronous sensors to send data. A set of handshaking signals facilitates the integration with an external DMA controller. The CSENT-RX core is designed with industry best practice, has been rigorously verified and is production proven.
By Computer Aided Software Technologies, Inc (dba CAST)
