100G UDP IP Stack
Logic Fruit’s 100G UDP IP Stack – Optimized for high-speed 100G data transfer with minimal CPU dependency. Fully supports ARP and ICMP for reliable network connectivity and easy integration into SoC designs
By Logic Fruit Global Technologies Inc
10GBASE-R PHY FPGA IP
The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.
By Altera
10GBASE-R PHY FPGA IP
The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.
By Altera
10GbE TCP Offloading Engine IP core (TOE10G-IP)
10GbE TCP Offloading Engine (TOE10G) IP core is the epochal solution implemented without CPU. Typically, TCP/IP stack consumes high valuable resource of CPU workloads. With its pure hardware logic, TOE10G IP can entirely take over the TCP/IP stack operation with high proven throughput for 10GbE communication.
By DesignGateway Co., Ltd.
12G SDI-FMC Daughter Card
The SDI-FMC is a FMC interfaced 12G SDI daughter card. Besides SDI, it also includes AES (Audio Engineering Society) audio interface and clock generators.
By Terasic Inc.
1G/10Gb Ethernet PHY FPGA IP
The 1G/10G Ethernet PHY Altera FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA).
By Altera
1GbE TCP Offloading Engine IP core (TOE1G-IP)
The TCP Offloading Engine (TOE1G) IP core is an innovative, CPU-free solution for TCP/IP processing. Traditionally, TCP handling is complex and requires expensive high-end CPUs. TOE1G-IP offloads all TCP/IP functions to pure hardware logic, enabling high-speed performance without software overhead.
By DesignGateway Co., Ltd.
25G Ethernet FPGA IP
The 25G Ethernet IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. This IP core optionally includes unidirectional transport and Reed-Solomon Forward Error Correction (FEC) for support of direct attach copper (DAC) cable.
By Altera
3D LUT Altera® FPGA IP
The 3D Look-Up Table (LUT) Altera® FPGA IP, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance, resource-efficient solution for video color space conversion, dynamic range adjustment, chroma keying, and artistic effect generation, enabling superior image quality in broadcast and professional video applications.
By Altera