Current: xSPI Initiator core.
xSPI Memory Controller Core for PSRAM, NOR Flash, STT-MRAM. Protocols: (a) JEDEC xSPI Profile 1.0, 2.0; (b) HyperBus 1.0, 2.0, 3.0; (c) OctaBus; (d) Octal Bus; (e) Exccela Bus. SLL support x8 and x16 PSRAM devices, and support chaining two x16 PSRAM devices to create x32 PSRAM channel.
By Synaptic Laboratories Ltd
CXL 3 CONTROLLER IP
The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for advanced systems. It supports multiple channels and configurable CXL degraded modes, ensuring seamless integration with CXL devices and enabling high-performance data transfer. Ideal for versatile system designs, it accommodates all three CXL device types to facilitate efficient connectivity and scalable architecture.
By Logic Fruit Global Technologies Inc
Cyclone® 10 GX FPGA Development Kit
The Cyclone® 10 GX Development Kit is a cost-effective platform for transceiver-based applications, featuring high-speed I/O and robust memory support.
By Altera
Cyclone® 10 LP FPGA Development Kit
The Cyclone® 10 LP Evaluation Kit is a low-cost, low-power platform ideal for entry-level FPGA development and education.
By Altera
Cyclone® V E FPGA Development Kit
The Cyclone® V E FPGA Development Kit offers a comprehensive general purpose development platform for Cyclone V FPGAs, and features an abundance of interactive options.
By Altera
Cyclone® V GT FPGA Development Kit
The Cyclone® V GT FPGA Development Kit provides a robust platform for evaluating high-speed transceiver capabilities of the Cyclone V GT FPGA, featuring PCIe Gen2 x4 and DDR3 support.
By Altera
Cyclone® V SX SoC Development Kit
The Cyclone® V SX SoC Development Kit offers a complete SoC FPGA platform with integrated ARM Cortex-A9 processors, ideal for embedded system development and hardware/software co-design.
By Altera
Data Management & CI/CD for FPGA
As an ICT service provider for the high-tech electronics design flow we offer data management solutions for developing firmware, and making sure that the code is complete and secured. We have developed solutions where the firmware is automatically built using makefiles using a clean build and several quality checks are performed on the completeness of the code.
By Dizain-Sync B.V.
DDR5 and DDR4, LPDDR5 and LPDDR4 External Memory Interfaces FPGA IP
DDR4 and DDR5 offer higher bandwidth and improved performance over previous generations, with DDR5 providing further enhancements in speed and power efficiency. LPDDR4 and LPDDR5 are optimized for low power consumption, making them ideal for embedded applications, with LPDDR5 offering even faster data rates and improved energy management. When integrated with Altera FPGAs these memory technologies enable faster data processing and more efficient power usage for a wide range of applications including networking, cloud and edge.
By Altera