HDMI-FMC Daughter Card
Terasic HDMI-FMC is a HDMI transmitter/receiver daughter board with FMC (FPGA Mezzanine card) interface. The user can connect the HDMI module with the FPGA development kit via the FMC connector for HDMI image & video capturing, processing and displaying up to 4Kx2K@30fps resolution.
By Terasic Inc.
High Dynamic Range (HDR) IP - using single exposure
Real-time, high-quality HDR IP with virtually zero latency, based on a single exposure. The IP is designed for FPGAs and can be embedded seamlessly in Gidel’s modular vision/imaging grabbing and image processing systems, which include PCIe boards and edge computers supporting GigE Vision, CoaXPress, Camera Link, and user-defined protocols.
By Gidel
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HiPrAcc™ CS200D Dual-Agilex™ Computational Storage Module
Highest performance PCIe Computational Storage Accelerator card with two Intel Agilex AGF027 FPGAs. up to 64TB on-card NVMe storage (8x M.2 SSDs) and Gen4 PCIe switch (Broadcom) interconnect.
By Hitek Systems LLC
HiPrAcc™ NC220 Low Profile PCIe Accelerator Card
Low-profile PCIe accelerator for data centers and edge AI, with up to 400 Gbps Ethernet, x16 PCIe Gen4, Agilex™ 7 FPGAs (006 through 027 density), 24/12 GB DDR4 and SMB PPS sync input
By Hitek Systems LLC
HiPrAcc™ NCS200 Networked Computational Storage Card
FPGA accelerator card featuring Agilex™ 7 Series FPGA with x16 Gen4 PCIe, 4x 100G networking interfaces, four on-card Gen4 M.2 NVMe SSDs (22110 and 2280) and two DDR4 UDIMM/RDIMM/LRDIMM slots — ideal for SmartNIC, computational storage and signal/image processing.
By Hitek Systems LLC
HiPrAcc™ NCS280-I CXL/PCIe Gen5 Accelerator
High performance CxL/PCIe Gen5 accelerator with R-Tile, dual QSFP28 based Ethernet networking, and dual on-card Gen4 M.2 NVMe SSDs
By Hitek Systems LLC
HSDLC: HDLC & SDLC Protocol Controller Core
The HSDLC IP core implements HDLC and SDLC protocols, based on the Intel® 8XC152 GSC in SDLC mode with added HDLC and proprietary frame support. It connects as a peripheral to a host processor via APB or 80C51-like interfaces, with full interrupt support for efficient operation. Flexible design allows two independent TX/RX interfaces with support for full- or half-duplex, hardware flow control (RTS/CTS), collision detection, and programmable baud rates. Receive clock is derived from incoming data or supplied externally. Available in Normal and Safety-Enhanced (TMR, DO-254 DAL-A) versions, the HSDLC core is fully synchronous, scan-ready, verified, and delivered in Verilog RTL or FPGA netlist. Deliverables include scripts, testbench, and complete documentation.
By Computer Aided Software Technologies, Inc (dba CAST)
I2S-TDM: I2S/TDM Multichannel Audio Transceiver
The I2S-TDM IP core is a configurable, full-duplex, multi-channel serial audio transceiver supporting both Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) interfaces. It can operate as either controller (master) or target (slave), exchanging audio samples over programmable serial lines. Designers can configure parameters such as sample width (2–32 bits), sample rate, frame format, number of channels, and allocation per line at run time, while synthesis-time options define maximum supported channels and lines. Integration is simplified with APB or AXI4-Lite control interfaces and AXI4-Stream for audio data, with clean clock domain crossings. The core is delivered as Verilog RTL or FPGA netlist, with testbench, scripts, drivers, and documentation, and typically uses about 10K gates for an 8-channel configuration.
By Computer Aided Software Technologies, Inc (dba CAST)
InfiniVision: Multi-Camera Frame Grabbing
The InfiniVision IP for Gidel FPGA grabber boards is designed for synchronized image acquisition from multiple cameras (100+). Its innovative architecture offers efficient data acquisition for high-bandwidth and high-frame-rate applications, as well as inline real-time compression. InfiniVision supports GigE Vision, CoaXPress, Camera Link, and proprietary user camera protocols.
By Gidel