Interlaken IP
Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond.
By Altera
IP Core Design and Development
IP Core Development & Customization
By System Level Solutions, Inc
ISDB-S3 demodulator
The Commsonic CMS0071 ISDB-S3 Demodulator is a high-performance (A)PSK demodulator core intended for ARIB STD-B44 ISDB-S3 advanced wideband digital satellite standard.
By Commsonic Ltd
ISDB-S3 modulator
The CMS0070 ISDB-S3 (A)PSK modulator is an integrated modulator and channel-coder core designed specifically to address the requirements of the ARIB STD-B44 advanced wide-band digital satellite broadcasting Standard.
By Commsonic Ltd
ISDB-T Modulator
The ISDB-T modulator / ISDB-TB modulator core enables rapid development of audio and visual systems using commodity free-to-air set-top-box products.
By Commsonic Ltd
Jedec xSPI Controller (Silicon Proven IP for Altera Devices)
Mobiveil’s xSPI Controller supports JEDEC-compliant NOR/NAND Flash and HyperRAM devices, enabling ultra-fast read throughput via x4/x8 SPI interfaces. It functions as a universal controller—SPI, Quad-SPI, Octa-SPI, or Dual-QSPI—ensuring backward compatibility with legacy devices. Designed for space-constrained, low-power applications, it supports multiple chip-selects and is ideal for wearables, cameras, and automation systems.
By Mobiveil Inc.
JESD204 FPGA IP
Altera JESD204 IP is a high-performance, JEDEC-compliant interface solution designed to simplify and accelerate the integration of high-speed data converters with digital processing systems. Supporting data rates up to 32.44 Gbps, it efficiently manages the physical, data link, and transport layers while offering pre-verified design examples and intuitive configuration, significantly reducing development time. Its robust clock synchronization and interoperability features ensure reliable, standards-based performance across demanding applications.
By Altera
JESD204B TRANSMITTER AND RECEIVER IP
Logic Fruit's JESD204B RTL IP supports increased lane rates up to 12.5Gbps for higher bandwidth applications. It can be configured to transmit or receive using a 8B10B link layer to achieve deterministic latency, SerDes synchronization, clock recovery and DC balance.
By Logic Fruit Global Technologies Inc
