HDMI IP Core
The HDMI Altera® FPGA IP core delivers high-performance, standards-compliant support for the latest HDMI specifications, enabling seamless transmission of high-definition audio and video over a single interface. It provides a robust and flexible solution for integrating next-generation video display connectivity into Altera FPGA designs.
By Altera
High Dynamic Range (HDR) IP - using single exposure
Real-time, high-quality HDR IP with virtually zero latency, based on a single exposure. The IP is designed for FPGAs and can be embedded seamlessly in Gidel’s modular vision/imaging grabbing and image processing systems, which include PCIe boards and edge computers supporting GigE Vision, CoaXPress, Camera Link, and user-defined protocols.
By Gidel
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HSDLC: HDLC & SDLC Protocol Controller Core
The HSDLC IP core implements HDLC and SDLC protocols, based on the Intel® 8XC152 GSC in SDLC mode with added HDLC and proprietary frame support. It connects as a peripheral to a host processor via APB or 80C51-like interfaces, with full interrupt support for efficient operation. Flexible design allows two independent TX/RX interfaces with support for full- or half-duplex, hardware flow control (RTS/CTS), collision detection, and programmable baud rates. Receive clock is derived from incoming data or supplied externally. Available in Normal and Safety-Enhanced (TMR, DO-254 DAL-A) versions, the HSDLC core is fully synchronous, scan-ready, verified, and delivered in Verilog RTL or FPGA netlist. Deliverables include scripts, testbench, and complete documentation.
By Computer Aided Software Technologies, Inc (dba CAST)
I2S-TDM: I2S/TDM Multichannel Audio Transceiver
The I2S-TDM IP core is a configurable, full-duplex, multi-channel serial audio transceiver supporting both Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) interfaces. It can operate as either controller (master) or target (slave), exchanging audio samples over programmable serial lines. Designers can configure parameters such as sample width (2–32 bits), sample rate, frame format, number of channels, and allocation per line at run time, while synthesis-time options define maximum supported channels and lines. Integration is simplified with APB or AXI4-Lite control interfaces and AXI4-Stream for audio data, with clean clock domain crossings. The core is delivered as Verilog RTL or FPGA netlist, with testbench, scripts, drivers, and documentation, and typically uses about 10K gates for an 8-channel configuration.
By Computer Aided Software Technologies, Inc (dba CAST)
InfiniVision: Multi-Camera Frame Grabbing
The InfiniVision IP for Gidel FPGA grabber boards is designed for synchronized image acquisition from multiple cameras (100+). Its innovative architecture offers efficient data acquisition for high-bandwidth and high-frame-rate applications, as well as inline real-time compression. InfiniVision supports GigE Vision, CoaXPress, Camera Link, and proprietary user camera protocols.
By Gidel
Interlaken IP
Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond.
By Altera
ISDB-S3 demodulator
The Commsonic CMS0071 ISDB-S3 Demodulator is a high-performance (A)PSK demodulator core intended for ARIB STD-B44 ISDB-S3 advanced wideband digital satellite standard.
By Commsonic Ltd
ISDB-S3 modulator
The CMS0070 ISDB-S3 (A)PSK modulator is an integrated modulator and channel-coder core designed specifically to address the requirements of the ARIB STD-B44 advanced wide-band digital satellite broadcasting Standard.
By Commsonic Ltd
ISDB-T Modulator
The ISDB-T modulator / ISDB-TB modulator core enables rapid development of audio and visual systems using commodity free-to-air set-top-box products.
By Commsonic Ltd