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eCPRI FPGA IP

Altera eCPRI FPGA IP implements the eCPRI 2.0 specification, providing a high-performance front-haul interface for next-generation radio base stations. It enables seamless, low-latency connectivity between eCPRI Radio Equipment Control (eREC) and Radio Equipment (eRE) over front-haul transport networks, accelerating deployment of scalable, flexible 5G infrastructure.

FFT FPGA IP Cores

The Fast Fourier transform (FFT) FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor.

FIR II FPGA IP Core

The FIR II IP cores provide a fully-integrated finite impulse response (FIR) filter function optimized for use with Altera FPGA devices.

GTS Ethernet Hard IP

The GTS Ethernet Hard IP (EHIP) allows fast, flexible, and high-performance Ethernet implementation with minimal FPGA resource utilization. The EHIP includes a configurable, hardened protocol stack for Ethernet compatible with the IEEE 802.3-2018 Standard and the 25G/50G Ethernet Specification from the 25 Gigabit Ethernet Consortium.

H16450S: UART with Synchronous CPU Interface

The H16450S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16450 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. Developed for easy reuse in ASIC and FPGA applications, the H16450S is available optimized for several technologies with competitive utilization and performance characteristics.

H16550S: Synchronous 16550 UART with FIFO Core

The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. The H16550S can be run in either 16450-compatible character mode or in 16550-compatible FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead. Developed for easy reuse in FPGA or ASIC applications, the H16550S is available optimized for several technologies with competitive utilization and performance characteristics.

H16750S: UART with FIFOs, IrDA and Synchronous CPU Interface

The H16750S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices. The H16750S can be run in either 16450-compatible character mode or FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead. An IrDA-compliant serial data port may be used for infrared communication. Developed for easy reuse in FPGA or ASIC applications, the H16750S is available optimized for several technologies with competitive utilization and performance characteristics

H264-E-BPF - Ultra-fast, AVC/H.264 Baseline Profile Encoder

The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. The H264-E-BPF encoder requires less silicon area than most equally capable hardware H.264 encoders—approximately 250K gates—allowing for very cost-effective implementations. Its small silicon footprint, low external memory bandwidth requirements, and zero software overhead enable high-throughput H.264 coding at an extremely low energy cost.

HBM2E (High-Bandwidth Memory) FPGA IP

HBM2E is a high-performance memory IP that offers a combination of high memory bandwidth, low power consumption, low latency, and small form factor for Agilex™ 7 FPGA M-Series devices. HBM2E memory is well-suited for various high-performance computing applications.