Jedec xSPI Controller (Silicon Proven IP for Altera Devices)
Mobiveil’s xSPI Controller supports JEDEC-compliant NOR/NAND Flash and HyperRAM devices, enabling ultra-fast read throughput via x4/x8 SPI interfaces. It functions as a universal controller—SPI, Quad-SPI, Octa-SPI, or Dual-QSPI—ensuring backward compatibility with legacy devices. Designed for space-constrained, low-power applications, it supports multiple chip-selects and is ideal for wearables, cameras, and automation systems.
By Mobiveil Inc.
JESD204 FPGA IP
Altera JESD204 IP is a high-performance, JEDEC-compliant interface solution designed to simplify and accelerate the integration of high-speed data converters with digital processing systems. Supporting data rates up to 32.44 Gbps, it efficiently manages the physical, data link, and transport layers while offering pre-verified design examples and intuitive configuration, significantly reducing development time. Its robust clock synchronization and interoperability features ensure reliable, standards-based performance across demanding applications.
By Altera
JESD204B TRANSMITTER AND RECEIVER IP
Logic Fruit's JESD204B RTL IP supports increased lane rates up to 12.5Gbps for higher bandwidth applications. It can be configured to transmit or receive using a 8B10B link layer to achieve deterministic latency, SerDes synchronization, clock recovery and DC balance.
By Logic Fruit Global Technologies Inc
JESD204C TRANSMITTER AND RECEIVER IP
Logic Fruit's JESD204C RTL IP supports increased lane rates upto 32Gbps for higher bandwidth applications. This IP can be configured to transmit or receive using either a 64B66B or 8B10B link layer with improved efficiency of payload delivery, and also provides for an improved robustness of the link with a backward-compatible option to JESD204B.
By Logic Fruit Global Technologies Inc
JESD204D TRANSMITTER AND RECEIVER IP
The main goal of this JEDEC Standard, JESD204D is to increase the lane rates to support even higher bandwidth applications needs and to add extra features.
By Logic Fruit Global Technologies Inc
JPEG-D-S: Baseline JPEG Decoder
The JPEG-D-S IP core is a compact, high-performance hardware JPEG decoder supporting the Baseline Sequential DCT mode of ISO/IEC 10918-1. It decompresses JPEG images and Motion-JPEG payloads, handling 8-bit samples and up to 4 components in all common subsampling formats. Processing 1 sample/cycle, it can decode multiple Full-HD channels even in cost-sensitive FPGAs. One of the smallest decoders, it uses about 4,000 ALMs in Altera FPGAs. Once programmed, it operates standalone, parsing markers and decompressing without host intervention. It reports resolution, subsampling, and depth for proper post-processing or display. Integration is simple via AMBA®: AXI Streaming for pixels/data and a 32-bit APB slave for registers. CAST offers integration services delivering complete JPEG subsystems with decoders, video interfaces, networking stacks, or other IP. Designed with best practices, its proven reliability is backed by verification, production use, and a bit-accurate software model.
By Computer Aided Software Technologies, Inc (dba CAST)
JPEG-DX-F: Ultra-Fast Baseline and Extended JPEG Decoder
This JPEG decompression IP core supports the Baseline & Extended Sequential DCT modes of the ISO/IEC 10918-1. It is scalable and ultra-high-performance, while handles extremely high pixel rates of JPEG images and video payload for Motion-JPEG container formats. It accepts compressed streams of images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. It can process from 2 to 32 color samples per clock cycle. Paired with the JPEG-EX-F Encoder Core provide an extremely cost-effective solution. Standalone operation, once programmed, parsing marker segments, decompressing coded data and reporting back the image format. SoC integration is straightforward (standard AMBA I/F - AXI Streaming & APB Slave). CAST’s IP Integration Services are also available for JPEG subsystems (the JPEG decoder with video interface controllers, Hardware UDPIP or Transport Stream networking stacks, or other IP cores available from CAST).
By Computer Aided Software Technologies, Inc (dba CAST)
JPEG-DX-S: Baseline and Extended JPEG Decoder
The JPEG-DX-S IP core is an area-efficient high-performance JPEG decoder supporting Baseline and Extended Sequential DCT modes of ISO/IEC 10918-1. It decodes JPEG and Motion-JPEG payloads, supporting 8- or 12-bit samples and up to four components in standard subsampling formats. Processing one sample per cycle, it can handle multiple Full-HD channels in cost-sensitive FPGAs. One of the smallest available, it requires ~76k gates in ASICs. Once configured, the core runs standalone, parsing markers and decompressing without host intervention. It reports resolution, subsampling, and depth for correct post-processing. Integration is simple via AMBA®: AXI-Stream for pixels/data and a 32-bit APB for registers. CAST offers integration services delivering complete JPEG subsystems (decoders, video interfaces, networking stacks, etc.). Designed to industry best practices, quality is proven by verification, silicon validation, and a bit-accurate software model. Scan-ready, LINT-clean, production.
By Computer Aided Software Technologies, Inc (dba CAST)
JPEG-E-S: Baseline JPEG Encoder
The JPEG-E-S IP core supports the Baseline Sequential DCT modes of ISO/IEC 10918-1, implementing a high-performance, area-efficient hardware JPEG encoder with low latency. It produces compressed JPEG images and Motion-JPEG payloads, handling 8-bit color samples and up to four components in all common subsampling formats. Processing one sample per cycle, it can compress multiple Full-HD channels even in low-cost FPGAs. Once configured, it operates standalone without host intervention. Integration is simple via AMBA®: AXI Streaming for pixels/compressed data and a 32-bit APB slave for registers. Optional AXI Streaming allows timestamps or metadata insertion. CAST offers IP Integration Services delivering complete JPEG subsystems with video interfaces, UDP/IP or Transport Stream stacks, and other IP. Designed with industry best practices, its reliability is proven through verification, production use, and a bit-accurate software model.
By Computer Aided Software Technologies, Inc (dba CAST)