UVM training
The Universion Verification Method (UVM) is the leading verification framework for digital design. Our UVM training offering teaches all aspects of the UVM framework, how it works, and how to apply it in your designs. It is configurable to include the necessary knowledge on Verilog and SystemVerilog that is used as the basis.
By Dizain-Sync B.V.
VHDL training
For more than 20 years we provide the best classroom training on VHDL in the Benelux. Our Professional VHDL training gives a very good foundation for professionals who want to start with VHDL. For the more advanced topics we have our Advanced VHDL training that will discuss advanced cases to bring your VHDL knowledge to the next level.
By Dizain-Sync B.V.
Video and Vision Processing Suite
The Altera FPGA Video and Vision Processing Suite is a collection of next-generation Altera intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs.
By Altera
Virtualyzr™ Pre-Silicon Verification (HW)
The Virtualyzr Side Channel Analysis license enables security evaluation of a design implementation at the pre-silicon level, before launching any foundry operation.
By Secure-IC SAS
Viterbi IP Core
The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implement a wide range of standard Viterbi decoders.
By Altera