Turbo-V FPGA IP Core
Turbo codes assist in forward error correction systems. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise.
By Altera
UDPIP-100G: 100G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 100 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.
By Computer Aided Software Technologies, Inc (dba CAST)
UDPIP-1G: UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 10 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.
By Computer Aided Software Technologies, Inc (dba CAST)
UDPIP-40G/50G: 40G/50G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 50 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.
By Computer Aided Software Technologies, Inc (dba CAST)
USB 10Gbps Device Controller (USB32SF)
10Gbps Device IP Core
By System Level Solutions, Inc
USB 2.0 Device with FIFO Interface (USB20HF)
USB20HF IP Core
By System Level Solutions, Inc
USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
USB20SR IP Core
By System Level Solutions, Inc
USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)
USB20SF IP Core
By System Level Solutions, Inc
