Warp FPGA IP
The Altera Warp FPGA IP core, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance solution for applying geometric corrections and non-linear transformations to real-time video streams.
By Altera
XAUI PHY FPGA IP
The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.
By Altera
XIP1113B: AES256-GCM IP core
Balanced speed AES256-GCM core implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with few Gpbs linerates.
By Xiphera Ltd.
XIP1113E: AES-GCM Authenticated Encryption, Extreme-Speed
Extreme speed AES256-GCM core implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with up to 800G linerate.
By Xiphera Ltd.
XIP1113H: AES256-GCM high-speed IP core
High speed AES256-GCM core implements the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with few tens of Gpbs linerates.
By Xiphera Ltd.
XIP1123B: Versatile AES256 IP core (ECB, CBC, CFB, OFB, CTR)
Xiphera’s Versatile AES IP core implements the Advanced Encryption Standard (AES) with a 256-bit key in five selectable modes: ECB, CBC, CFB, OFB, and CTR.
By Xiphera Ltd.
XIP1183B: Balanced AES256-XTS IP Core
AES-XTS IP cores implement the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode.
By Xiphera Ltd.
XIP1183H: AES256-XTS high-speed IP Core
AES-XTS IP cores implement the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode.
By Xiphera Ltd.
XIP1213B: MACSEC AES256-GCM IP core targeting 1Gbps+ links
MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model.
By Xiphera Ltd.