Serial Lite IP
The Serial Lite FPGA IP core is a simple, low-latency, scalable protocol for high-bandwidth serial data transfer applications. It is suitable for high-bandwidth data communication for chip-to-chip, board-to-board, and backplane applications. The core incorporates a media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) block.
By Altera
Stratix 10 FPGA H-Tile Hard IP for Ethernet
The Stratix 10 H-Tile Ethernet Hard IP core is available with a 100GBASE-R4 Ethernet channel. For the Ethernet data rate, you can choose a media access control (MAC) + physical coding sublayer (PCS) variation or a PCS-only variation.
By Altera
TCPIP-100G: 100G TCP/UDP/IP Hardware Stack
The TCPIP-1G/10G core is a complete hardware TCP/IP stack that supports up to 32k sessions, DHCP, UDP with multicast, and offers configurable low-latency cut-through or reliable store-and-forward modes.
By Computer Aided Software Technologies, Inc (dba CAST)
Tone Mapping Operator FPGA IP
The Tone Mapping Operator (TMO) FPGA IP corrects poorly exposed images and video to reveal invisible details.
By Altera
Triple-Speed Ethernet FPGA IP
A complete 10/100/1000 Mbps Ethernet IP with flexible IP options including MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA.
By Altera
TSN-EP: TSN Ethernet Endpoint Controller
The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS-2020) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.3br) and a low-latency Ethernet MAC. Enhanced reliability features can also be sup ported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci).
By Computer Aided Software Technologies, Inc (dba CAST)
TSN-SE: TSN Ethernet Switched Endpoint Controller
"The TSN-SE is a highly configurable two-port Switched Endpoint Controller IP core tailored for Time-Sensitive Networking (TSN) Ethernet systems. It embeds hardware support for 802.1AS-2020 timing synchronization, 802.1Qav/Qbv traffic shaping, 802.1Qbu/802.3br frame preemption, plus two low-latency Ethernet MACs. Optional modules enable enhanced reliability with 802.1CB frame replication and elimination, and 802.1Qci per-stream filtering and policing. Designed for daisy-chained or ring topologies and bridged endpoints, TSN-SE delivers precise, deterministic ingress/egress latency via cut-through switching and minimal buffering, simplifying time-aware application development. It provides real-time timing data timestamps, alarms, and allows dynamic traffic-shaping configuration. Integration is seamless via standard AMBA® interfaces: a 32-bit APB bus for control/status, and 32-bit AXI-Streaming for packet I/O. Optional DMA engine and software stacks are also available.
By Computer Aided Software Technologies, Inc (dba CAST)
Turbo-V FPGA IP Core
Turbo codes assist in forward error correction systems. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise.
By Altera
UDPIP-100G: 100G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack enabling high-speed LAN or point-to-point communication and media streaming up to 100 Gbps, even in processor-less SoC designs. Offloads the host CPU from UDP/IP encapsulation. All network parameters (IP addresses, UDP ports, MAC) are runtime programmable, supporting static or DHCP-assigned IP. Includes ARP for multi-access networks, ICMP ping for connectivity tests, and IEEE 802.1Q VLAN tagging. Supports up to 32 transmit and 32 receive streaming interfaces (channels), each independently configurable for IP, port, multicast address, and unicast/multicast mode. Integrates easily in SoC designs via AXI4-Stream, Avalon-ST, AHB, AXI, Avalon-MM, or Wishbone interfaces, with data exchange via streaming ports or memory-mapped registers. Ideal for real-time networking, video streaming, and industrial applications requiring low-latency, deterministic UDP/IP communication in FPGA or ASIC designs.
By Computer Aided Software Technologies, Inc (dba CAST)