PTP Timestamp Unit (IEEE1588 – Precision Time Protocol)
PTP Timestamp Unit
By NetTimeLogic GmbH
PTP Transparent Clock (IEEE1588 – Precision Time Protocol)
Full standalone hardware only solution of a PTP Transparent Clock
By NetTimeLogic GmbH
Quality+ IP - 1:10 video compression preserves image SNR
Gidel’s Quality+ (Q+) IP targeting FPGA compresses Color Filter Array (CFA – e.g., Bayer), Monochrome, and RGB images and videos in real-time. Q+ revolutionizes image compression, achieving up to 1:10+ compression ratios for high-bandwidth image streams while preserving original image quality.The Quality+ IP can be embedded seamlessly in Gidel's image acquisition systems, including the Gidel frame grabbers and compact edge computers. The compression supports high-end camera streaming, including 10+ GigE Vision, CoaXPress and Camera Link. Gidel's real-time compression IPs are particularly beneficial for high-bandwidth and high-resolution imaging and vision applications enabling to improve image quality while increasing recording time, reducing storage size, and reducing post recording data offload and compression time on host computer.
By Gidel
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Real-Time JPEG Compression IP
Gidel’s real-time JPEG image compression (encoder) IP enables high-performance JPEG compression on FPGA. The compression IP is unique in its fast processing capacity, low latency, and compact silicon utilization. As a result of its compactness, the IP can be implemented on a small FPGA device to compress high-performance camera image streams or, alternatively, instantiated multiple times on a single larger FPGA device. The JPEG IP can be embedded seamlessly in Gidel's image acquisition systems, including the Gidel frame grabbers and compact edge computers. The compression supports high-end camera streaming, including 10+ GigE Vision, CoaXPress and Camera Link. Gidel's real-time compression IPs are particularly beneficial for high-bandwidth and high-resolution imaging application enabling increased recording time, reduces storage size, and reduced post recording data offload and compression time on host computer.
By Gidel
Reed Solomon II FPGA IP Core
The Reed Solomon II IP offers a fully parameterizable Reed Solomon encoder and decoder.
By Altera
SATA 3 Controller IP
Logic Fruit's SATA 3 Controller IP enables fast and efficient connectivity for storage devices, supporting high-speed data transfer. It works seamlessly with both newer and older SATA interfaces.
By Logic Fruit Global Technologies Inc
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SCR: Smart Card Reader Controller
Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces. The SCR supports the ISO/IEC 7816-3:2006 and EMV 4.3 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions.
By Computer Aided Software Technologies, Inc (dba CAST)
SDI II FPGA IP
The Altera SDI II FPGA IP core enables high-performance serial digital interface (SDI) transmission and reception across SD, HD, and 3G to 12G video rates.
By Altera
Securyzr™ iSE Root of Trust solutions
Securyzr™ iSE is Secure-IC Root of Trust solution. Embedded in an FPGA or SOC designs, it offers multiple services to its host system: secure boot, key isolation, anti-tampering protection, etc. Thanks to its dual computation and strong isolation, it offers an additional layer of security compared to trusted execution environments.
By Secure-IC SAS
