HBM2E (High-Bandwidth Memory) FPGA IP
HBM2E is a high-performance memory IP that offers a combination of high memory bandwidth, low power consumption, low latency, and small form factor for Agilex™ 7 FPGA M-Series devices. HBM2E memory is well-suited for various high-performance computing applications.
By Altera
HDMI IP Core
The HDMI Altera® FPGA IP core delivers high-performance, standards-compliant support for the latest HDMI specifications, enabling seamless transmission of high-definition audio and video over a single interface. It provides a robust and flexible solution for integrating next-generation video display connectivity into Altera FPGA designs.
By Altera
Interlaken IP
Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond.
By Altera
JESD204 FPGA IP
Altera JESD204 IP is a high-performance, JEDEC-compliant interface solution designed to simplify and accelerate the integration of high-speed data converters with digital processing systems. Supporting data rates up to 32.44 Gbps, it efficiently manages the physical, data link, and transport layers while offering pre-verified design examples and intuitive configuration, significantly reducing development time. Its robust clock synchronization and interoperability features ensure reliable, standards-based performance across demanding applications.
By Altera
Low Latency Ethernet 100G MAC and PHY FPGA IP
Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block.
By Altera
Low Latency Ethernet 10G MAC FPGA IP
The Low Latency Ethernet 10G MAC FPGA IP core offers low round-trip latency and efficient resource footprint. This IP core offers programmability of various features listed. It can be used in conjunction with the Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.
By Altera
LVDS Tunneling Protocol and Interface IP
LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.
By Altera
MIPI D-PHY IP
Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.
By Altera
Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration.
By Altera