XIP7013E: IPSEC AES-256-GCM
IPsec (Internet Protocol Security) is a widely implemented protocol to secure communications across the Internet. Xiphera’s Ipsec extreme speed IP core enhances secure communication at layer three (Network) of the OSI model, ensuring the authenticity and confidentiality of data traffic with up to 400G linerates.
By Xiphera Ltd.
XIP7410B: nQrux® Secure Boot
nQrux® Secure Boot enhances system security by enabling quantum-secure authenticated boot, crucial for verifying the authenticity and integrity of binary images during the processor boot sequence.
By Xiphera Ltd.
XIP8001B True Random Number Generator (TRNG) IP Core
The True Random Number Generator (TRNG) IP core establishes a benchmark for hardware-based security in cryptographic systems, by generating high-entropy, true random numbers essential for secure communications and cryptographic operations, such as key generation.
By Xiphera Ltd.
XIP8103B Pseudo Random Number Generator (PRNG) IP Core, balanced version
Xiphera’s Pseudorandom Number Generator (PRNG) IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers.
By Xiphera Ltd.
XIP8103H Pseudo Random Number Generator (PRNG) IP Core, high-speed version
Xiphera’s Pseudorandom Number Generator (PRNG) IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers.
By Xiphera Ltd.
xSPI-MC: xSPI, HyperBus™, and Xccela™ Serial Memory Controller
The xSPI-MC is a versatile memory controller supporting JEDEC xSPI, HyperBus™, and Xccela™ standards, as well as proprietary SPI protocols for Flash and PSRAM. It enables easy device detection, direct boot, and operation in multiple modes: Slave (AHB slave access), DMA (with internal DMA engine), Access In-Place (AIP) via AHB/AXI, and Boot-Image copy after reset. Compatible with single to 16x SPI devices, it offers flexible configuration through registers or an auto-configuration feature using a device list. Highly customizable via Verilog defines, it allows selection of DMA, auto-configuration, and device count. Delivered with a synthesizable soft-PHY, it is FPGA/ASIC ready and requires no process-specific dependencies.
By Computer Aided Software Technologies, Inc (dba CAST)
⚡Flapmax FMAX Inference
Sovereign AI inference engine scaling from server to datacenter for low-latency, energy-efficient performance.
By FLAPMX LLC
🚙 Flapmax NV Drive Platform
Neuromobility vehicle (NV) platform integrating AI retrofits, fleet intelligence, and national transport resilience.
By FLAPMX LLC