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LVDS Tunneling Protocol and Interface IP

LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.

MIPI D-PHY IP

Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.

Multi-Rate Ethernet PHY FPGA IP

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration.

NCO FPGA IP Core

Numerically Controlled Oscillator IP for discrete-time, discrete-valued representation of a sinusoidal waveform.

Nios V Processors

Nios® V processors are the next generation of soft processor IPs, designed to bring the power and flexibility of the open-source RISC-V Architecture to FPGA environments. By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.

nQrux® Crypto Module

Xiphera’s nQrux® Crypto Module IP core provides a comprehensive security platform that allows for customisation of top-notch cryptographic services, suitable for both microcontrollers and SoC systems.

NTP Client

Full standalone hardware only solution of a NTP Client

NTP Server

Full standalone hardware only solution of a NTP Server

NVMe Controller (Silicon Proven IP for Altera Devices)

The NVMe Controller is a configurable and UNH-certified solution for enterprise and client PCIe SSDs, featuring multi-core and lock-free architecture. It includes NVMe-aware DMA engines, firmware-controlled command handling, and supports AXI and proprietary interfaces. Integrated with Mobiveil’s GPEX or third-party NAND controllers, it achieves optimized latency, throughput, and efficiency.