Turbo-V FPGA IP Core
Turbo codes assist in forward error correction systems. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise.
By Altera
Video and Vision Processing Suite
The Altera FPGA Video and Vision Processing Suite is a collection of next-generation Altera intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs.
By Altera
Viterbi IP Core
The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implement a wide range of standard Viterbi decoders.
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Warp FPGA IP
The Altera Warp FPGA IP core, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance solution for applying geometric corrections and non-linear transformations to real-time video streams.
By Altera
XAUI PHY FPGA IP
The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.
By Altera