Xiphera’s Pseudorandom Number Generator (PRNG) IP core establishes a benchmark for hardware-based security in cryptographic systems by generating high-quality pseudorandom numbers. It delivers accelerated output rates essential for secure communications and cryptographic operations, such as key generation. It includes robust and thoroughly characterised initialisation and reseeding mechanisms and a proven CTR_DRBG and AES-256 based pseudorandom number generator.
Xiphera Ltd.
Key Features
- High Performance: XIP8103H can achieve over 69 Gbps throughput, while consuming only about 18000 Lookup Tables (LUTs) in a typical FPGA implementation.
- Versatility: XIP8103H supports the forward prediction resistance mode, which can be set on and off between output generation, as well as the use of personalization strings and additional inputs for instantiation and reseeding.
- Standard Compliance: XIP8103H is compliant with the NIST SP800-90A specification [1]. XIP8103H can be combined with Xiphera’s NIST SP800-90B [3] compliant XIP8001B to form a NIST SP800-90C compliant [2] Random Bit Generator (RBG).
- Easy integration with AXI4-Lite and AXI stream interfaces.
Offering Brief
Offering Brief
| Device Family | Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® III FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | Yes |
| Latest Quartus Version Supported | 25.1.1 |
| Development Language | Encrypted VHDL, VHDL |
Encrypted RTL or source code
Optional netlist
Sample synthesis scripts
Instantiation file
Comprehensive simulation test bench, scripts & guide
Detailed datasheet and integration guide
Ordering Information
XIP8103H
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