MACsec is a point-to-point protocol located on layer two (Data Link) of the OSI model. Xiphera’s comprehensive MACsec solution portfolio safeguards the confidentiality and integrity of data transmitted over point-to-point communication links, assured by the Advanced Encryption Standard (AES) in Galois Counter Mode (GCM) with 256-bit key length.
Xiphera Ltd.
Key Features
- Moderate resource requirements: The entire XIP1213B requires 9907 Adaptive Lookup Modules (ALMs) (Altera® Cyclone® 10 GX), and does not require any multipliers or DSPBlocks in a typical FPGA implementation.
- Performance: XIP1213B achieves a throughput in the Gbps range3, for example 3.78 Gbps in AMD® Kintex® UltraScale+.
- Standard Compliance: XIP1213B is fully compliant with the MACsec protocol as standardized in IEEE Std 802.1AE-2018 [2]. The cipher suite (GCM-AES-256 or GCM-AES-XPN-256) is fully compliant with the Advanced Encryption Algorithm (AES) standard [1], as well as with the Galois Counter Mode (GCM) standard [3].
- Test Vector Compliance: XIP1213B passes the relevant test vectors speci€ed in Annex C of IEEE Std 802.1AE-2018 [2].
- 32-bit FIFO Interfaces ease the integration of XIP1213B with other FPGA logic and/or control software.
Offering Brief
Offering Brief
| Device Family | Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | Yes |
| Latest Quartus Version Supported | 25.1.1 |
| Development Language | Encrypted VHDL, VHDL |
Encrypted RTL or source code
Sample synthesis scripts
Optional netlist
Instantiation file
Comprehensive simulation test bench, scripts & guide
Detailed datasheet and integration guide
Ordering Information
XIP1213B
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