XIP1183H: AES256-XTS high-speed IP Core

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Xiphera Ltd.

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AES-XTS IP cores implement the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode. AES-XTS is a block-based encryption method primarily employed to secure data while it is stored, and the IP cores can be used to encrypt data on hard drives and other storage devices. High speed with linerates of tens of Gpbs

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Key Features

Moderate resource requirements: The entire XIP1183H requires 28456 Adaptive Lookup Modules (ALMs) (Altera® Agilex® 7 F), and does not require any multipliers or DSP Blocks
Performance: XIP1183H achieves an impressive throughput in the tens of Gbps range, for example 43.48+ Gbps in AMD® Versal® Prime.
Standard Compliance: XIP1183H is compliant with both the Advanced Encryption Algorithm (AES) standard [1] and the XTS standard [2]
Optional Ciphertext stealing support as defined in [2].
• Increased Performance can be achieved by parallel instantiations of XIP1183H.
Support for Burst-Mode Sector Writes and Reads with the default sector size of 4kB3.

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® III FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	Yes
Latest Quartus Version Supported	25.1.1
Development Language	Encrypted VHDL, VHDL