AES-XTS IP cores implement the Advanced Encryption Standard (AES) with a 256-bit key in XTS mode. AES-XTS is a block-based encryption method primarily employed to secure data while it is stored, and the IP cores can be used to encrypt data on hard drives and other storage devices.
Xiphera Ltd.
Key Features
- Moderate resource requirements: The entire XIP1183B requires 6079 Adaptive Lookup Modules (ALMs) (Intel® Agilex® F), and does not require any multipliers or DSPBlocks2.
- Performance: XIP1183B achieves an impressive throughput in the Gbps range, for example 3.20+ Gbps in Xilinx® Kintex® UltraScale+.
- Standard Compliance: XIP1183B is compliant with both the Advanced Encryption Algorithm (AES) standard [1], and the XTS standard [2] .
- Optional Ciphertext stealing support as defined in [2].
- Increase Performance can be achieved by paralle instantiations of XIP1183B.
Offering Brief
Offering Brief
| Device Family | Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | No |
| Evaluation License | No |
| Design Examples Available | No |
| Demo | No |
| Compliance | No |
| Latest Quartus Version Supported | 25.1.1 |
| Development Language | Encrypted VHDL, VHDL |
Encrypted RTL or source code
Sample synthesis scripts
Optional netlist
Instantiation file
Comprehensive simulation test bench, scripts & guide
Detailed datasheet and integration guide
Ordering Information
XIP1183B
from Direct
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