XIP1123B: Versatile AES256 IP core (ECB, CBC, CFB, OFB, CTR)

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Xiphera Ltd.

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Xiphera’s Versatile AES IP core implements the Advanced Encryption Standard (AES) with a 256-bit key in five selectable modes: ECB, CBC, CFB, OFB, and CTR. All of these modes ensure data confidentiality and are widely used in security designs and cryptographic protocols.

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Key Features

Moderate resource requirements: The entire XIP1123B requires 3891 Adaptive Lookup Modules (ALMs) (Intel® Agilex® F), and does not require any multipliers or DSPBlocks4.
Performance: XIP1123B achieves an impressive throughput in the Gbps range, for example 3.23+ Gbps in Xilinx® Kintex® UltraScale+.
Standard Compliance: XIP1123B is fully compliant with both the Advanced Encryption Algorithm (AES) standard [1], as well as with the ECB, CBC, CFB, OFB, and CTR modes of operation [2].
Versatility: The key, initialization vector (IV), and the mode of operation can dynamically updated for every 128-bit data block.

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	Yes
Latest Quartus Version Supported	25.1.1
Development Language	Encrypted VHDL, VHDL