The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implement a wide range of standard Viterbi decoders. Viterbi decoding (also known as maximum likelihood decoding or forward dynamic programming) is the most common way of decoding convolutional codes by using an asymptotically optimum decoding technique. In its basic form, Viterbi decoding is an efficient, recursive algorithm that performs an optimal exhaustive search. A convolutional encoder and Viterbi decoder are typically used together to provide error correction over a noisy channel. For example, a communications channel.
Altera
Key Features
- High-speed parallel architecture with performance of over 240 Mbps, fully parallel operation and enhanced block decoding and continuous decoding
- Low-speed to medium-speed, hybrid architecture, configurable number of add compare and select (ACS) units, memory-based architecture and a wide range of performance and logic area
- Fully parameterized Viterbi decoder, including: Number of coded bits, constraint length, number of soft bits, traceback length, polynomial for each coded bit and variable constraint length
- Modulation support with trellis coded modulation (TCM) option
- Trellis coded modulation (TCM) option
- VHDL testbenches to verify the decoder with Intellectual property (IP) functional simulation models for use in Altera FPGA-supported VHDL and Verilog HDL simulators
Offering Brief
Offering Brief
| Device Family | Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® IV E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | No |
| Development Language | Encrypted Verilog, Encrypted VHDL |
Encrypted Verilog source code
Design example
Simulation models
IP evaluation mode
Documentation: IP user guide, IP release notes
Ordering Information
IP-VITERBI/HS, IP-VITERBI/SS
from Mouser
IP-VITERBI/HS, IP-VITERBI/SS
from Mouser
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