USB 2.0 HUB (USB20HUB) IP Core

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

System Level Solutions, Inc

Select

USB 2.0 Hub IP core provides a link between the USB2.0 Host and multiple USB peripherals via UTMI + Low pin interface (ULPI). It supports High speed, Full speed and Low speed peripheral devices. Its rich features and ease of use makes it more suitable for embedded applications.

View Partner Website

Partner Product Page

Contact Now

Contact System Level Solutions, Inc

LeadSource

ASAP Account ID

Record Type Name

Key Features

Supports High speed, Full speed and Low speed peripheral devices.
Supports individual port power switching.
Remote wakeup capable.
Integrated Transaction Translator (TT).
Configurable Hub speed.
Configurable Transaction Translator buffers.
Supports Suspend and Resume.
Supports connect/disconnect detection of down-stream ports.
Supports standard as well as hub class-specific requests.
Supports UTMI + Low Pin interface (ULPI).
Reliable.
Easy to use.

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status	Production
Integrated Testbench	No
Evaluation License	Yes
Design Examples Available	Yes
Demo	Yes
Compliance	No
Latest Quartus Version Supported	25.1.0
OS Support	Windows,Linux
Development Language	Encrypted Verilog, Verilog