USB 2.0 Host Controller IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface. It supports High Speed (HS), Full Speed (FS) and Low Speed (LS) modes. IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as ready to use component and hence can be easily integrated in system.
System Level Solutions, Inc
Key Features
- Supports Low Speed (1.5 Mbps), Full Speed (12 Mbps) and High Speed (480 Mbps) modes
- Supports Control, Bulk and Interrupt transfers
- Contains two different interfaces for Control Port and Data Port to improve Clock Domain Crossing (CDC) performance
- Supports Asynchronous Avalon clock interface
- Supports SPLIT transfer
- Optimized TD (Transfer Descriptor) structure
- Configurable memory depth
- Supports UTMI + Low Pin interface (ULPI) interface
- Meets Design Assistant guidelines
Offering Brief
Offering Brief
| Device Family | Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | Yes |
| Compliance | No |
| Latest Quartus Version Supported | 25.1.0 |
| OS Support | Windows,Linux |
| Development Language | Encrypted Verilog, Verilog |
Encrypted IP Core
Reference Design
Reference Documents
Demo
HAL Driver in object form
Simulation Library
Ordering Information
USB 2.0 Host Controller - IPRUSB2SFP004
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Aerospace
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ASIC Proto
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Consumer
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Medical
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Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
Image
Test
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