Serial Lite IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The Serial Lite II FPGA IP core provides a simple and lightweight way to move data from one point to another reliably at high speeds. It consists of a serial link of up to 16 bonded lanes with logic to provide a number of basic and optional link support functions. The Atlantic* interface is the primary access for delivering and receiving data. The Serial Lite II protocol specifies a link that is simple to build, uses as little logic as possible, and requires little work to implement. The Serial Lite II FPGA IP is feature-rich, and can be parameterized through a powerful graphical user interface (GUI). The Serial Lite III IP Core is a simple, low-latency, scalable protocol for high-bandwidth serial data transfer applications. It offers simple connectivity that enables rapid point-to-point data transfers across various transmission media, including printed circuit board (PCB), backplane, copper cabling, and fiber optics. Serial Lite III includes technology-leading transceivers: physical medium attachment (PMA) layer, physical coding sublayer (PCS), and media access control (MAC) layer. The PCS and PMA layers are hardened within Stratix 10, Arria 10, Stratix V, and Arria V FPGAs to save customers valuable FPGA logic resources. The Serial Lite IV IP core also incorporates a MAC, PCS, and PMA block. It supports data transfer up to 58 Gbps per lane with a maximum of 12 PAM4 lanes of the Agilex 7 F-tile General-Purpose Transceivers (FGT), up to 116 Gbps with a maximum of 4 PAM4 lanes of the Agilex 7 F-tile High-Speed Transceivers (FHT) in a single link, up to 28 Gbps per lane with a maximum of 16 non-return-to-zero (NRZ) lanes of FGT, or up to 58 Gbps per lane with a maximum of 4 NRZ lanes of FHT. This protocol offers high bandwidth, low overhead frames, and low I/O count supporting high scalability in both numbers of lanes and speed. The IP is easily reconfigurable with support of a wide range of data rates with Ethernet PCS mode of the E-Tile transceiver and the F-Tile transceiver with our latest GTS transceivers for the Agilex 5 devices.

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Key Features

Serial Lite II: 622 Mbps to 6.375 Gbps per lane. Single or multiple lane support (up to 16 lanes). Full-duplex or self-synchronizing link state machine (LSM). Support for two user packet types: data packet and priority packet
Serial Lite III: Up to 28 Gbps lane data rate for Stratix 10 with H-tile or E-tile transceivers. Up to 17.4 Gbps lane data rates for Arria 10 devices. Supports 1–24 serial lanes in configurations that provide nominal bandwidths from 3.125 Gbps to over 400 Gbps. Up to 12.5 Gbps for Cyclone 10 GX devices
Serial Lite IV: Supports up to 116 Gbps per lane with a maximum of 4 PAM4 lanes of FHT in a single link. Supports up to 58 Gbps per lane with a maximum of 4 NRZ lanes of FHT in a single link. Supports up to 58 Gbps per lane with a maximum of 12 PAM4 lanes of FGT in a single link. Supports up to 28 Gbps per lane with a maximum of 16 NRZ lanes of FGT in a single link. Supports continuous streaming (Basic) or packet (Full) modes. Supports low overhead frame packets; Supports 64b/66b encoding decoding.

Offering Brief

Device Family	Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Encrypted Verilog