PTP Timestamp Unit (IEEE1588 – Precision Time Protocol)

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NetTimeLogic GmbH

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NetTimeLogic’s PTP Timestamp Unit (TSU) is an implementation of a single port Frame Timestamp Unit according to IEEE1588-2019/2008 (PTP). It detects PTP frames on the (R)(G)MII (tap or intercept) and timestamps PTP event frames and provides them delay compensated to a PTP Software stack (e.g. PTPd, PTP4l, etc…) and can also insert timestmaps into PTP frames for one-step mode. The Timestamp Unit can be used to build a PTP Ordinary Clock (OC) as Master and Slave; it can also be used to build a PTP Boundary Clock (BC) by having multiple instances of the IP core connected to multiple Ethernet ports.

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Key Features

PTP Timestamp Unit according to IEEE1588-2019/2008
PTP frame detection and PTP event frame timestamping
Taps path between MAC and PHY or intercepts path between MAC and PHY, Full line speed
Optional One Step support (requires intercepting the path between MAC and PHY)
Support for Layer 2 (Ethernet) and Layer 3 (Ip), VLAN, HSR and PRP, Peer to Peer (P2P) and End to End (E2E).
Master and Slave support
Configurable Interrupt
Optional 10G XGMII extension (requires add-on license)
Linux Driver, TSU driver part is independent from MAC driver (needs to be called though from the MAC driver)
PHY Delay compensation with automatic link speed detection

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Cyclone® IV E FPGA, Stratix® 10 AX SoC FPGA
Offering Status	Production
Demo	No
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Compliance	No
Intertop	ISPCS, IIC
Latest Quartus Version Supported	25.1.0
Development Language	C/C++, VHDL