Logic Fruit's PCIe GEN6 Controller IP delivers data speed up to 64GT/s (Gigatransfers per second) per lane. Multi-channel packet processing and enhanced RAS capabilities ensure data integrity and simplify system integration. Configurable for both Root Port and Endpoint use, it supports a wide range of applications such as high-performance computing, data centers, AI/ML, high-speed networking, to name a few.
Logic Fruit Global Technologies Inc
Key Features
- Full PCIe 6.x Specification Support: Compliant with all standard PCIe data rates: 2.5, 5, 8, 16, 32, and 64 GT/s.
- Backward Compatibility: Seamless support from Gen1 to Gen5, including equalization bypass transitions.
- x16 Link Width Support: Scalable link width for higher throughput and performance.
- Compatible with PIPE-6.x PHYs: Integrates with Logic Fruit’s PHY or third-party SerDes via PIPE 6.x interface.
- FLIT and Non-FLIT Mode Operation: Supports up to 4 Virtual Channels (VCs) in both modes for traffic class isolation.
- Advanced Error Correction: Includes Forward Error Correction (FEC) and End-to-End CRC (ECRC) for enhanced data integrity.
- Tx/Rx Cut-Through Support: Enables low-latency data transmission with early packet forwarding.
- High Payload Support: Supports MRRS and MPS as 4K, along with 4096-bit TLPs and 14-bit tag support.
- Root Port Configuration Support: Suitable for both Endpoint and Root Complex implementations.
- Integrated Power Management: Includes advanced state management, power states, and LTSSM monitoring.
- Synthesizable RTL and Example Designs: Delivered with testbenches, constraint files, and simulation scripts for quick integration.
- FPGA/ASIC Ready: Redy to be deployed across Tier 1 leaders.
Offering Brief
Offering Brief
| Device Family | Agilex® 7 FPGAs and SoC FPGAs I-Series, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | No |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | No |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Verilog, VHDL |
RTL Code: Available in encrypted format or complete synthesizable source code. Designed for integration with FPGAs or ASICs.
Configuration Tools: GUI-based interface and script-based environment to configure IP for different setups.
Example Designs.
Test Environment: Simulation test scripts for functional verification.
Documentation: Detailed User Guide, Functional Programming Guide and Step-by-step instructions for configuration, integration, and simulation.
Ordering Information
sales@logic-fruit.com
from Direct
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