The PCI-T32 implements a target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz PCI clock. The interface core implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required. The Target supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 4 GB. The Target supported commands are: • Configuration Read, Configuration Write • Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL), Memory Write and Invalidate (MWI) • I/O Read, I/O Write The PCI-T32 builds on more than 20 years of CAST PCI IP expertise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with e...
Computer Aided Software Technologies, Inc (dba CAST)
The PCI-T32 implements a target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz PCI clock. The interface core implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required. The Target supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 4 GB. The Target supported commands are: • Configuration Read, Configuration Write • Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL), Memory Write and Invalidate (MWI) • I/O Read, I/O Write The PCI-T32 builds on more than 20 years of CAST PCI IP expertise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with everything required for rapid and successful integration and implementation.
Key Features
- Fully compliant with PCI Local Bus Specification, Revision 2.3
- Operates at 33 MHz with a 32-bit PCI data path
- Zero wait state burst mode
- Implements full PCI Target functionality
- Supports a single interrupt line - Parity generation and parity error detection
- Type 0 Configuration Space implementation
- All Base Address Registers fully supported
- Optional bridge to AMBA/AHB or Avalon-MM available
Offering Brief
Offering Brief
| Device Family | Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Encrypted VHDL, Verilog, VHDL |
Verilog/System Verilog, Encrypted Verilog/System Verilog, VHDL, Encrypted VHDL, or FPGA netlist
Sample integration testbench
Comprehensive documentation
Sample synthesis and simulation scripts
Software model
Ordering Information
PCI-T32
from Direct
$0.00
.svg?h=0&itok=ZOeb-0LL)
