Multi-Rate Ethernet PHY FPGA IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration. This IP allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G. It handles the frame encapsulation and flow of data between a client logic and Ethernet network via PCS and PMA (PHY).

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Key Features

Implements the Ethernet protocol as defined in clause 36 of the IEEE 802.3 2005 standard
Consists of a physical coding sublayer (PCS) function and an embedded physical medium attachment (PMA)
Dynamically switchable PHY operating speed; 1G/2.5G, 2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G (MGBASE-T), 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M, 100M, 1G, 2.5G, and 10G (MGBASE-T) operating modes
Users needing Copper-PHY capability for USXGMII, MGBASE-T modes will need to use an external PHY chip
Avalon® memory-mapped interface for PHY management
Datapath client interface: 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
Datapath Ethernet interface: 10M/100M/1G/2.5G/5G/10G (USXGMII)—Single 10.3125 Gbps serial link

Offering Brief

Device Family	Arria® V GT FPGA, Arria® V GX FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 TX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Encrypted Verilog