Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional Forward Error Correction (FEC) block. It also includes IEEE 1588v2 timestamping support and the capability to drive backplanes on supported Stratix and Arria FPGAs. This IP can be used for chip-to-chip interfaces using copper interconnect or optical transceiver modules. The IP core is designed to the IEEE 802.3ba-2010 High-Speed Ethernet Standard, available on the IEEE website (www.ieee.org). The MAC provides cut-through frame processing to optimize latency, supports full wire line speed with a 64-byte frame length, and supports back-to-back or mixed length traffic with no dr...
Altera
Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional Forward Error Correction (FEC) block. It also includes IEEE 1588v2 timestamping support and the capability to drive backplanes on supported Stratix and Arria FPGAs. This IP can be used for chip-to-chip interfaces using copper interconnect or optical transceiver modules. The IP core is designed to the IEEE 802.3ba-2010 High-Speed Ethernet Standard, available on the IEEE website (www.ieee.org). The MAC provides cut-through frame processing to optimize latency, supports full wire line speed with a 64-byte frame length, and supports back-to-back or mixed length traffic with no dropped packets. All Low Latency 100G Ethernet IP core variations include full-duplex MAC and PHY components.
Key Features
- Soft PCS logic that interfaces seamlessly to Stratix 10 FPGA 25.78125 Gbps serial transceivers
- CAUI-4 external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps
- TX automatic frame padding to meet the 64-byte minimum Ethernet frame length
- Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers
- Avalon-ST datapath interface connects to client logic with the start of frame in the most significant byte (MSB)
- Hardware and software reset control
- RX CRC checking and error reporting
Offering Brief
Offering Brief
| Device Family | Arria® V GZ FPGA, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | No |
| Development Language | Encrypted Verilog |
Encrypted Verilog source code
Design Example
Simulation Models
IP Evaluation Mode
Documentation: IP User Guide, Design Example User Guide, IP Release Notes
Ordering Information
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Digikey
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Mouser
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Mouser
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Digikey
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Mouser
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Digikey
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Digikey
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Mouser
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Mouser
IP-100GEMAC; IP-100GEPHY; IP-100GEMACPHY; IP-100GEUMACPHY; IP-100GEUMACPHYF
from Digikey
Documentation & Resources
Market Segment and Sub-Segments
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