The LIN-CTRL core is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. It can be configured before the synthesis to operate as a master, slave or include both profiles. When configured with both – master and slave, then at run-time, the LIN-CTRL can operate either as a master or as a slave and supports versions 1.3, 2.0, 2.1, and 2.2 of the LIN protocol. The message transfers can be controlled via a microcontroller interface and a LIN transceiver is needed for the connection to the LIN bus. The LIN-CTRL core is a microcode-free design developed for reuse in ASIC and FPGA implementations. The scan-ready design is strictly synchronous with positive-edge clocking and no internal tri-states. The robustly verified core has been production-proven multiple times. The LIN controller core is available in two versions: Standard, and Safety-Enhanced. The Safety-Enhanced ...
Computer Aided Software Technologies, Inc (dba CAST)
The LIN-CTRL core is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. It can be configured before the synthesis to operate as a master, slave or include both profiles. When configured with both – master and slave, then at run-time, the LIN-CTRL can operate either as a master or as a slave and supports versions 1.3, 2.0, 2.1, and 2.2 of the LIN protocol. The message transfers can be controlled via a microcontroller interface and a LIN transceiver is needed for the connection to the LIN bus. The LIN-CTRL core is a microcode-free design developed for reuse in ASIC and FPGA implementations. The scan-ready design is strictly synchronous with positive-edge clocking and no internal tri-states. The robustly verified core has been production-proven multiple times. The LIN controller core is available in two versions: Standard, and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO-26262 ASIL-D Ready.
Key Features
- LIN Ctrl 1.3, 2.0, 2.1, and 2.2A LIN standards Operates as master, slave or both (defined at run-time) Data rate: 1 Kbit/s and 20 Kbit/s (for master)
- Integration 8-bit interface with APB and AHB wrappers Fully synchronous design Production-proven IP Core Synthesizes to approximate 4,400 to 5,900 gates
- Safety Enhanced Version (optional) ISO-26262 ASIL-D Ready Implements ECC for SRAM and redundancy – DMR or TMR, including optional lockstep operation
Offering Brief
Offering Brief
| Device Family | Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist
Sample integration testbench
System Verilog testbench
Comprehensive documentation
Sample synthesis and simulation scripts
Bare Metal Driver (on request and extra cost)
IPxact register models
Ordering Information
LIN-CTRL
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Documentation & Resources
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