Configurable LDPC Encoder/Decoder IP delivering industry-leading flash reliability and endurance with 50 MB/s to 9 GB/s single-instance scalability, low area/power, and support for multiple LDPC codes with on-the-fly switching. Mobiveil’s LDPC IP is a technology-independent, system-validated ECC block for flash controllers that scales from ultra-low-power mobile to enterprise SSD performance. Each instance is optimized for target codeword sizes, parity, and parallelism, with selectable memory access options and platform targets (eASIC/FPGA/40–10 nm ASIC). Deliverables include LDPC compiler & matrix-gen source, an FPGA LLR reference design (MATLAB interface), and a UVM env with encoder, error injector, and decoder.
Mobiveil Inc.
Key Features
- Scalable LDPC architecture supporting data rates from 50 MB/s to 9.0 GB/s per single instance.
- Flexible platform enabling customer-specific custom LDPC core generation.
- Optimized for a wide range of codeword sizes to suit diverse applications.
- Supports the maximum required parity for robust error correction.
- High degree of parallelism for achieving high data-rate performance.
- Multiple memory access options for integration flexibility.
- Platform-specific configurations available for eASIC, FPGA, and ASIC nodes from 40 nm to 10 nm.
- Simultaneous support for different amounts of parity in the same core.
- Simultaneous support for multiple LDPC codes.
- On-the-fly switching between LDPC codes without system reset.
- Low area footprint for cost-sensitive designs.
- Low power consumption suitable for both mobile and enterprise applications.
Offering Brief
Offering Brief
| Device Family | Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, eASIC™ N3X Devices, eASIC™ N3XS Devices, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | No |
| Demo | No |
| Compliance | No |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Source Code for LDPC Compiler
Source Code for LDPC Matrix Generation Software
FPGA based LLR generation reference design with MATLAB interface
UVM verification env with encoder, error injector and decoder instantiated
IP User Guide
Synthesis Guide
Ordering Information
NA
from Direct
Documentation & Resources
Market Segment and Sub-Segments
ASIC Proto
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Consumer
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Data Center Cloud (Public, Private, Hybrid)
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Data Center OEM (IHV, ISV, SI, VAR)
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Industrial
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Transportation
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Automotive (Passenger Vehicles)
Transportation Infrastructure (non-charging)
Wireless
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