Logic Fruit Technologies JESD204D IP core delivers enhanced lane rates to meet the growing bandwidth demands of high-performance applications. Designed with backward compatibility for JESD204C and JESD204B, our IP core ensures seamless integration with existing systems.
Logic Fruit Global Technologies Inc
Key Features
- Designed according to JEDEC JESD204D Standard
- Supports up to 24 lanes per IP cores
- Supports new link layer using Reed-Solomon Forward Error Correction (RS-FEC)
- Option for backward compatibility to JESD204C (supports 64B/66B encoding) and JESD204B (supports 8B/10B encoding)
- Transport layer to support multi ADC/DAC synchronization and multiple lanes
- Data interfaces up to 116 Gbps with PAM4 encoding and up to 58 Gbps with NRZ encoding
- Supports subclass 0,1 and 3
- Supports all the new features introduced in JESD204D specifications
Offering Brief
Offering Brief
| Device Family | Arria® 10 SX SoC FPGA, Arria® 10 GT FPGA, Arria® V GZ FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | No |
| Evaluation License | No |
| Design Examples Available | No |
| Demo | No |
| Compliance | No |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | VHDL |
All the new features introduced in JESD204D specifications
Option for backward compatibility with JESD204C (64b/66b) and JESD204B (8b/10b) link layers
Ordering Information
sales@logic-fruit.com
from Direct
Market Segment and Sub-Segments
Aerospace
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Defense
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Medical
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Test
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