Logic Fruit Technologies has designed JESD204C RTL IP to support increased lane rates up to 32Gbps for higher bandwidth applications. This IP can be configured to transmit or receive using either a 64B66B or 8B10B link layer with improved efficiency of payload delivery and also provides for improved robustness of the link with a backward-compatible option to JESD204B.
Logic Fruit Global Technologies Inc
Key Features
- With the addition of error correction(FEC), cutting-edge instrumentation and other applications can operate without any errors.
- Offers better DC balance, clock recovery and data alignment compared to JESD204B.
- The bit overhead is 3.125% which is much smaller than JESD204B (~ 25%).
- Provides interface for serializing devices from some system designs, reducing space, power, and cost.
- It supports interface requirements of high megabit and Gigabit data rates for various applications such as 5G cellular equipments, test equipments, medical devices, military warfare and so on.
- Mechanism to achieve Deterministic latency across the serial link.
Offering Brief
Offering Brief
| Device Family | Arria® 10 SX SoC FPGA, Arria® 10 GT FPGA, Arria® V GZ FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | No |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | No |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Verilog, VHDL |
VHDL/Verilog Design Files
VHDL Test Bench
VHDL Testcases
Log Files of Simulation Results
Ordering Information
sales@logic-fruit.com
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Market Segment and Sub-Segments
Aerospace
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Defense
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Medical
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Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
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