Interlaken IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The Interlaken FPGA IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high-bandwidth throughput in their systems. This pre-built, ready-to-go IP building block shortens the design cycle resulting in faster time to market. Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond. The Interlaken FPGA IP core is ideal for: 1) Multi-terabit routers and switches for access, 2) Carrier Ethernet and data center applications that demand IP configurability to optimize for various traffic profiles, and 3) Scalability for next-generation platforms. The Altera Interlaken IP Portfolio accomplishes major development milestones: third-generation soft IP (includes media access control (MAC)) and second-generation hardened IP (includes physical coding sublayer (P...

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Key Features

Data rate selection up to 25.78125 Gbps (NRZ) OR 56 Gbps (PAM4)
Multi-lane configuration up to 24 lanes
Interleave packet mode support
Programmable meta frame lengths
Fully integrated IP (MAC, PCS, and PMA layers)
Multi-segment or Start-of-Packet (SOP) alignment user interface options
Up to 256 logical channels
Advanced error handling and error injection capabilities
Supports Interlaken Look-Aside mode
I/O controllable burst settings (Min, Max, Short)

Offering Brief

Device Family	Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	No
Demo	No
Compliance	No
Development Language	Encrypted Verilog