The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver. The transceiver can act as a controller (master) or a target (slave) for Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) audio interfaces, exchanging multi-channel audio samples over a configurable number of serial lines (pins). The I2S-TDM offers a number of configuration options to satisfy a wide range of serial audio interface requirements. The operation mode (controller or target), sample width, sample rate, frame format, number of channels and their allocation to physical lines are all programmable at run time. At synthesis time, designers can choose the maximum number of audio channels and serial data lines the transceiver can support. The core is designed for ease of use and integration and adheres to the industry’s best coding and verification practices. The core’s control and status registers (CSR) are accessed through a 32-bit AMBA® APB interfac...
Computer Aided Software Technologies, Inc (dba CAST)
The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver. The transceiver can act as a controller (master) or a target (slave) for Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) audio interfaces, exchanging multi-channel audio samples over a configurable number of serial lines (pins). The I2S-TDM offers a number of configuration options to satisfy a wide range of serial audio interface requirements. The operation mode (controller or target), sample width, sample rate, frame format, number of channels and their allocation to physical lines are all programmable at run time. At synthesis time, designers can choose the maximum number of audio channels and serial data lines the transceiver can support. The core is designed for ease of use and integration and adheres to the industry’s best coding and verification practices. The core’s control and status registers (CSR) are accessed through a 32-bit AMBA® APB interface, or, optionally, an AXI4 Lite interface. The host system exchanges audio data with the core either via this CSR interface or via dedicated AXI4-Stream interfaces. The system interfaces operate with a clock that is independent from the audio master and serial bit clocks, and the core implements clean clock domain crossing boundaries. The I2S-TDM core is available in Verilog source code or as a targeted FPGA netlist. Its deliverables include a testbench, comprehensive documentation, sample simulation and synthesis scripts, and bare-metal device drivers.
Key Features
- Supports I2S/TDM formats with left/right justification, full-duplex transmit/receive, and configurable audio channels and data lines
- Master/slave modes with 2–32 bit samples, adjustable rate & frame format, plus flexible channel mapping across data lines
- Set Tx/Rx lines, max audio channels, and FIFO sizes at synthesis to optimize performance, latency, and resource use
- APB/AXI4-Lite for control, 32-bit AXI-Stream for audio I/O, with maskable FIFO-based interrupts for efficient, reliable streaming
Offering Brief
Offering Brief
| Device Family | Stratix® V GS FPGA, Stratix® V GX FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | Yes |
| Latest Quartus Version Supported | 24.3.1 |
| Development Language | Encrypted Verilog, Verilog |
Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist
Sample integration testbench
Sample synthesis and simulation scripts
Comprehensive documentation
Bare Metal Driver
Ordering Information
I2S-TDM
from Direct
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