CPRI FPGA IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The Common Public Radio Interface (CPRI) Altera® FPGA IP core implements the CPRI Specification V7.0. CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE). The IP core targets high-performance, remote radio network applications. You can configure the CPRI Altera® FPGA IP core as an RE or an REC.

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Key Features

Compliant with the Common Public Radio Interface (CPRI) Specification v7.0 (2015-10-09) Interface Specification,
Supports radio equipment controller (REC) and radio equipment (RE) module configurations, Configurable CPRI line bit rate auto-rate negotiation support using Altera® FPGA on-chip high-speed transceivers,
Configurable and runtime programmable synchronization mode: host port or agent port on a CPRI link, Transmitter (Tx) and receiver (Rx) deterministic latency and delay measurement and calibration.
Configurable and runtime programmable synchronization mode: host port or agent port on a CPRI link.
Transmitter (Tx) and receiver (Rx) deterministic latency and delay measurement and calibration. Note: Compliant with the CPRI Specification requirements R-19, R-20, R-20A, R-21, and R-21A.
Configurable CPRI communication line bit rate (to 0.6144, 1.2288, 2.4576, 3.0720, 4.9152, 6.144, 8.11008, 9.8304, 10.1376, 12.16512 or 24.33024 Gbps) using Altera® FPGA on-chip high-speed transceivers.

Offering Brief

Device Family	Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Arria® V GX FPGA, Arria® V GT FPGA, Arria® V GZ FPGA, Cyclone® V GX FPGA, Cyclone® V GT FPGA, Stratix® V GX FPGA, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 GX FPGA, Stratix® 10 DX FPGA, Stratix® 10 AX SoC FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Verilog, VHDL