An IP core that accepts a sampled high-bandwidth RF input stream and separates it into multiple lower-bandwidth output streams that each cover a portion of the input RF spectrum.
Bit by Bit Signal Processing LLC
Key Features
- Highly parallel
- High FMax
- Resource-efficient
- Supports non-power-of-2 channelizer bins
- Supports real-to-complex channelizers
Offering Brief
Offering Brief
| Device Family | Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | Yes |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | No |
| Compliance | No |
| Latest Quartus Version Supported | 24.3.0 |
| Development Language | Verilog |
Verilog code
Documentation
Examples
Tests that can be run by the customer
Test results
Synthesis results
Performance curves
Support
Ordering Information
BxBChan
from Direct
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