Backplane Ethernet 10GBASE-KR PHY FPGA IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The Backplane Ethernet 10GBASE-KR PHY Altera FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate both the hard standard physical coding sublayer (PCS), the higher performance hard 10G PCS, and the hard physical medium attachment (PMA) for a single Backplane Ethernet channel. It implements the functionality described in the IEEE 802.3ap-2007 standard. Because each instance of the 10GBASE-KR PHY IP core supports a single channel, you can create multichannel designs by instantiating more than one instance of the core.

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Key Features

Integrated 1000BASE-KX / 10GBASE-KR (1G/10Gb) Backplane Ethernet PCS and PMA
Direct internal interface with Altera FPGA 1G/10GbE media access controller (MAC) for a complete single-chip solution
10GBASE-KR Auto-Negotiation for negotiating between 1000BASE-KX (1 Gbps Ethernet or 1GbE) and 10GBASE-KR (10 Gbps Ethernet or 10GbE) PHY types per clause 73 of the IEEE 802.3ap-2007 standard
Forward error correction (FEC) to minimize retransmission in accordance to IEEE 802.3 and 802.3ba clause 74
Internal programmable algorithm for the receiver adaptation process per IEEE 8023.ap clause 72.6.10.2.3 for ease of use
Receiver-link fault status detection
Local serial loop-back from transmitter to receiver at the serial transceiver for self test
High-performance internal system interfaces: 1) GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE MAC, 8 bits at 125 MHz and 72 bits at 156.25 MHz respectively for data transfer. 2)Avalon Memory-Mapped (PDF) (Avalon-MM) 32-bit interface for agent management
Link Training to automatically configure the remote link partner transmitter physical media driver (PMD) for the lowest bit error rate (BER) per clause 72 of IEEE 802.3ap-2007 standard
Flexible IP user controls for performance optimization in various system configurations and channels

Offering Brief

Device Family	Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Encrypted Verilog