Altera

About Altera

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Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation.

Our innovation of programmable logic started in 1983 in Silicon Valley. In 1984, Altera unveiled the world’s first programmable logic device capable of being programmed, erased, and reprogrammed altering the future of innovation.

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Warp FPGA IP Intellectual Property (IP) Interfaces Audio / Video

The Altera Warp FPGA IP core, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance solution for applying geometric corrections and non-linear transformations to real-time video streams.

SDI II FPGA IP Intellectual Property (IP) Interfaces Audio / Video

The Altera SDI II FPGA IP core enables high-performance serial digital interface (SDI) transmission and reception across SD, HD, and 3G to 12G video rates.

3D LUT Altera® FPGA IP Intellectual Property (IP) Digital Signal Processing / AI Video and Image Processing

The 3D Look-Up Table (LUT) Altera® FPGA IP, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance, resource-efficient solution for video color space conversion, dynamic range adjustment, chroma keying, and artistic effect generation, enabling superior image quality in broadcast and professional video applications.

HDMI IP Core Intellectual Property (IP) Digital Signal Processing / AI Interfaces Audio / Video Video and Image Processing

The HDMI Altera® FPGA IP core delivers high-performance, standards-compliant support for the latest HDMI specifications, enabling seamless transmission of high-definition audio and video over a single interface. It provides a robust and flexible solution for integrating next-generation video display connectivity into Altera FPGA designs.

Tone Mapping Operator FPGA IP Intellectual Property (IP) Interfaces Audio / Video

The Tone Mapping Operator (TMO) FPGA IP corrects poorly exposed images and video to reveal invisible details.

Video and Vision Processing Suite Intellectual Property (IP) Digital Signal Processing / AI Interfaces Audio / Video Video and Image Processing

The Altera FPGA Video and Vision Processing Suite is a collection of next-generation Altera intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs.

HBM2E (High-Bandwidth Memory) FPGA IP Intellectual Property (IP) Interfaces

HBM2E is a high-performance memory IP that offers a combination of high memory bandwidth, low power consumption, low latency, and small form factor for Agilex™ 7 FPGA M-Series devices. HBM2E memory is well-suited for various high-performance computing applications.

Agilex™ 3 FPGA and SoC C-Series Development Kit Acceleration / AI / Cloud Boards / SOMs / Dev Kits Data Processing / Analysis / Acquisition Development / Evaluation Kit Edge Neural Network PCI Express Public / On Premise

Agilex™ 3 FPGA and SoC C-Series Development Kit is a compact, power-efficient platform for embedded and edge applications, featuring DisplayPort 1.4, dual MIPI interfaces, and Raspberry Pi HAT expansion.

Nios V Processors Intellectual Property (IP) Soft Embedded Processors

Nios® V processors are the next generation of soft processor IPs, designed to bring the power and flexibility of the open-source RISC-V Architecture to FPGA environments. By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.

JESD204 FPGA IP Intellectual Property (IP) Interfaces Transceivers & Basic Functions Clocks, PLLs and Resets Transceivers

Altera JESD204 IP is a high-performance, JEDEC-compliant interface solution designed to simplify and accelerate the integration of high-speed data converters with digital processing systems. Supporting data rates up to 32.44 Gbps, it efficiently manages the physical, data link, and transport layers while offering pre-verified design examples and intuitive configuration, significantly reducing development time. Its robust clock synchronization and interoperability features ensure reliable, standards-based performance across demanding applications.

DDR5 and DDR4, LPDDR5 and LPDDR4 External Memory Interfaces FPGA IP Intellectual Property (IP) Memory Controllers SDRAM

DDR4 and DDR5 offer higher bandwidth and improved performance over previous generations, with DDR5 providing further enhancements in speed and power efficiency. LPDDR4 and LPDDR5 are optimized for low power consumption, making them ideal for embedded applications, with LPDDR5 offering even faster data rates and improved energy management. When integrated with Altera FPGAs these memory technologies enable faster data processing and more efficient power usage for a wide range of applications including networking, cloud and edge.

eCPRI FPGA IP Intellectual Property (IP) Interfaces Communication Ethernet High Speed Networking / Security

Altera eCPRI FPGA IP implements the eCPRI 2.0 specification, providing a high-performance front-haul interface for next-generation radio base stations. It enables seamless, low-latency connectivity between eCPRI Radio Equipment Control (eREC) and Radio Equipment (eRE) over front-haul transport networks, accelerating deployment of scalable, flexible 5G infrastructure.

O-RAN FPGA IP Intellectual Property (IP) Digital Signal Processing / AI Interfaces Memory Controllers Transceivers & Basic Functions Communication Ethernet Modulation Networking / Security Simulation, Debug and Verification Transceivers

Altera O-RAN IP delivers a flexible, standards-compliant fronthaul interface for 5G and LTE systems using the 7-2x functional split. Supporting both control and user planes per O-RAN-FH.CUS.0-v03.00, it simplifies DU-RU integration, accelerates development, and ensures interoperability in disaggregated, open RAN architectures.

Serial Lite IP Intellectual Property (IP) Interfaces Serial

The Serial Lite FPGA IP core is a simple, low-latency, scalable protocol for high-bandwidth serial data transfer applications. It is suitable for high-bandwidth data communication for chip-to-chip, board-to-board, and backplane applications. The core incorporates a media access control (MAC), physical coding sublayer (PCS), and physical media attachment (PMA) block.

CPRI FPGA IP Intellectual Property (IP) Digital Signal Processing / AI Interfaces Transceivers & Basic Functions Communication Error Correction Ethernet High Speed Modulation Networking / Security Transceivers

Altera CPRI FPGA IP delivers a high-performance, standards-compliant implementation of the CPRI Specification V7.0, enabling reliable, high-speed communication between Radio Equipment Controllers (RECs) and Remote Radio Equipment (REs). Fully configurable as either REC or RE, the IP simplifies integration in remote radio network applications and accelerates deployment of robust, low-latency fronthaul links.

Low Latency Ethernet 100G MAC and PHY FPGA IP Intellectual Property (IP) Interfaces Ethernet

Altera offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet FPGA IP core targeted to network infrastructure and data centers. The Low Latency 100G Ethernet FPGA IP core is compliant with the IEEE 802.3ba-2010 Standard. It includes a media access control (MAC), PHY, physical coding sublayer (PCS), physical medium attachment (PMA), and an optional forward error correction (FEC) block.

Interlaken IP Intellectual Property (IP) Interfaces High Speed Networking / Security

Interlaken is an interconnect protocol for high-speed, channelized chip-to-chip interface in networking applications. It is optimized for high-bandwidth chip-to-chip packet transfers at rates from 10 Gbps to 600 Gbps and beyond.

50G Ethernet FPGA IP Intellectual Property (IP) Interfaces Ethernet

The 50G Ethernet FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium and the IEEE 802.3by 25Gb Ethernet draft. The IP core provides standard media access control (MAC), physical coding sublayer (PCS), and PMA functions. The PHY comprises the PCS and PMA.

Stratix 10 FPGA H-Tile Hard IP for Ethernet Intellectual Property (IP) Interfaces Ethernet

The Stratix 10 H-Tile Ethernet Hard IP core is available with a 100GBASE-R4 Ethernet channel. For the Ethernet data rate, you can choose a media access control (MAC) + physical coding sublayer (PCS) variation or a PCS-only variation.

25G Ethernet FPGA IP Intellectual Property (IP) Interfaces Ethernet

The 25G Ethernet IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium. This IP core optionally includes unidirectional transport and Reed-Solomon Forward Error Correction (FEC) for support of direct attach copper (DAC) cable.

40G Ethernet MAC and PHY FPGA IP Intellectual Property (IP) Interfaces Ethernet

The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010. 40 Gbps Ethernet is an industry standard and is compliant for media access control (MAC) and PHY (PCS+PMA) functions. It enables an FPGA to interface to another device over a copper or optical transceiver module.

Agilex 7 and Stratix 10 FPGA E-Tile Hard IP Intellectual Property (IP) Interfaces Ethernet

The Agilex 7 and Stratix 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium. The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps.

Low Latency Ethernet 10G MAC FPGA IP Intellectual Property (IP) Interfaces Ethernet

The Low Latency Ethernet 10G MAC FPGA IP core offers low round-trip latency and efficient resource footprint. This IP core offers programmability of various features listed. It can be used in conjunction with the Multi-Rate PHY FPGA IP core to support the range of 10M/100M/1G to 10G data rates.

Agilex 7 F-Tile Ethernet Hard IP Intellectual Property (IP) Interfaces Ethernet

The Agilex 7 FPGA F-Tile IP core implements Ethernet at data rates of 10 Gbps, 25 Gbps, 40 Gbps, 50 Gbps, 100 Gbps, 200 Gbps and 400 Gbps. The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation.

Multi-Rate Ethernet PHY FPGA IP Intellectual Property (IP) Interfaces Ethernet

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration.

10GBASE-R PHY FPGA IP Intellectual Property (IP) Interfaces Memory Controllers Transceivers & Basic Functions Clocks, PLLs and Resets Compute Express Link (CXL) Ethernet Flash High Speed PCI Express (IP) SDRAM Simulation, Debug and Verification SRAM Transceivers

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

1G/10Gb Ethernet PHY FPGA IP Intellectual Property (IP) Interfaces Ethernet

The 1G/10G Ethernet PHY Altera FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA).

GTS Ethernet Hard IP Intellectual Property (IP) Interfaces Ethernet

The GTS Ethernet Hard IP (EHIP) allows fast, flexible, and high-performance Ethernet implementation with minimal FPGA resource utilization. The EHIP includes a configurable, hardened protocol stack for Ethernet compatible with the IEEE 802.3-2018 Standard and the 25G/50G Ethernet Specification from the 25 Gigabit Ethernet Consortium.

Backplane Ethernet 10GBASE-KR PHY FPGA IP Intellectual Property (IP) Interfaces Memory Controllers Transceivers & Basic Functions Ethernet

The Backplane Ethernet 10GBASE-KR PHY Altera FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate the hard standard physical coding sublayer (PCS), the higher performance hard 10G PCS, and the hard physical medium attachment (PMA) for a single Backplane Ethernet channel.

Viterbi IP Core Intellectual Property (IP) Digital Signal Processing / AI Error Correction

The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implement a wide range of standard Viterbi decoders.

Triple-Speed Ethernet FPGA IP Intellectual Property (IP) Interfaces Ethernet

A complete 10/100/1000 Mbps Ethernet IP with flexible IP options including MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA.

Turbo-V FPGA IP Core Intellectual Property (IP) Digital Signal Processing / AI Error Correction

Turbo codes assist in forward error correction systems. You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise.

FFT FPGA IP Cores Intellectual Property (IP) Interfaces Memory Controllers Ethernet Flash SDRAM SRAM

The Fast Fourier transform (FFT) FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor.

NCO FPGA IP Core Intellectual Property (IP) Digital Signal Processing / AI Modulation

Numerically Controlled Oscillator IP for discrete-time, discrete-valued representation of a sinusoidal waveform.

Reed Solomon II FPGA IP Core Intellectual Property (IP) Digital Signal Processing / AI Error Correction

The Reed Solomon II IP offers a fully parameterizable Reed Solomon encoder and decoder.

FIR II FPGA IP Core Intellectual Property (IP) Digital Signal Processing / AI Memory Controllers Floating Point

The FIR II IP cores provide a fully-integrated finite impulse response (FIR) filter function optimized for use with Altera FPGA devices.

5G LDCPC-V FPGA IP Intellectual Property (IP) Digital Signal Processing / AI Error Correction

Low-density parity-check (LDPC) IP helps transmit and receive messages over noisy channels. This IP implements LDPC codes compliant with the 3rd generation partnership project 5G specification.

LVDS Tunneling Protocol and Interface IP Acceleration / AI / Cloud Intellectual Property (IP) Data Processing / Analysis / Acquisition Interfaces Transceivers & Basic Functions Clocks, PLLs and Resets Communication Ethernet High Speed Serial Simulation, Debug and Verification Transceivers

LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.

CIC FPGA IP Core Intellectual Property (IP) Digital Signal Processing / AI Modulation

The CIC FPGA IP core offers computationally efficient cores for extracting baseband signals.

XAUI PHY FPGA IP Intellectual Property (IP) Interfaces Transceivers & Basic Functions Clocks, PLLs and Resets Communication Ethernet High Speed Networking / Security Serial Simulation, Debug and Verification Transceivers

The XAUI PHY IFPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module. You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.

10GBASE-R PHY FPGA IP Intellectual Property (IP) Interfaces Transceivers & Basic Functions Ethernet

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

Agilex™ 7 FPGA F-Series Development Kit (P-Tile and E-Tile) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Data Science Development / Evaluation Kit Edge Machine Learning PCI Express Public / On Premise

The Agilex™ 7 FPGA F-Series Development Kit (P-Tile and E-Tile) is a flexible platform for Agilex 7 F-Series FPGA evaluation, featuring PCIe Gen4 and DDR4 support.

MIPI D-PHY IP Acceleration / AI / Cloud Intellectual Property (IP) Artificial Intelligence (AI) Digital Signal Processing / AI Edge Interfaces Machine Learning Neural Network Artificial Intelligence Audio / Video Error Correction Filters /Transforms Floating Point Modulation Video and Image Processing

Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.

Stratix® 10 SX SoC Development Kit Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Data Science Development / Evaluation Kit Edge Machine Learning PCI Express Public / On Premise

The Stratix® 10 SX SoC Development Kit accelerates advanced SoC development utilizing high-bandwidth memory and versatile I/O

Stratix® 10 TX Signal Integrity Development Kit Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Data Science Development / Evaluation Kit Edge Machine Learning

The Stratix® 10 TX Signal Integrity Development Kit enables 58 Gbps PAM4 transceiver evaluation with SMA and QSFP-DD connectivity.

Stratix® 10 GX Signal Integrity Development Kit (H-TILE) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Data Science Development / Evaluation Kit Edge Machine Learning PCI Express Public / On Premise

The Stratix® 10 GX Signal Integrity Development Kit (H-TILE) is designed for high-speed transceiver and signal integrity testing, featuring 28 Gbps and 56 Gbps transceiver support and advanced measurement capabilities.

Stratix® 10 GX FPGA Signal Integrity Development Kit (L-TILE) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Data Science Development / Evaluation Kit Edge Machine Learning PCI Express Public / On Premise

The Stratix® 10 GX FPGA Signal Integrity Development Kit (L-TILE) is designed for high-speed transceiver and signal integrity testing, featuring 28 Gbps and 56 Gbps transceiver support and advanced measurement capabilities.

Stratix® V GX FPGA Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit PCI Express

The Stratix® V GX FPGA Development Kit is a flexible platform for high-performance FPGA development, featuring Stratix V GX FPGAs and support for PCIe and high-speed serial interfaces.

Stratix® V GX Transceiver SI Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit

The Stratix® V GX Transceiver SI Development Kit offers a complete platform for signal integrity testing, featuring Stratix V GX FPGAs and support for up to 12.5 Gbps transceiver data rates.

Stratix® V GS DSP Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit PCI Express

The Stratix® V GS DSP Development Kit provides a complete design environment that includes all the hardware and software you need to begin developing DSP-intensive FPGA designs in a PCIe form factor

Stratix® V GX 100G Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit

The Stratix® V GX 100G Development Kit is a high-bandwidth platform for 100G Ethernet applications, featuring a Stratix V GX FPGA and integrated 100G MAC/PHY reference designs.

MAX® 10 FPGA Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit

The MAX® 10 FPGA Development Kit is a versatile platform for system-level FPGA development, featuring embedded flash and dual ADCs.

MAX® V CPLD Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit

The MAX® V CPLD Development Kit provides a low-cost, flexible platform for evaluating MAX V CPLDs, featuring a compact design and abundant connectivity options for rapid prototyping.

MAX® 10 FPGA 10M08 Evaluation Kit (POWER SOL'N 2) Boards / SOMs / Dev Kits Development / Evaluation Kit

The MAX® 10 FPGA 10M08 Evaluation Kit (POWER SOL'N 2) provides a low-cost, entry-level platform for evaluating the MAX 10 FPGA family, featuring integrated flash and ADCs.

MAX® 10 FPGA 10M50 Evaluation Kit Boards / SOMs / Dev Kits Daughter Card

The MAX® 10 FPGA 10M50 Evaluation Kit is a compact, yet feature-rich platform for prototyping, offering a variety of connectivity options including HDMI

MAX® 10 FPGA 10M08 Evaluation Kit (POWER SOL'N 1) Boards / SOMs / Dev Kits Development / Evaluation Kit

The MAX® 10 FPGA 10M08 Evaluation Kit (POWER SOL'N 1) provides a low-cost, entry-level platform for evaluating the MAX 10 FPGA family, featuring integrated flash and ADCs.

Arria® 10 GX FPGA Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit PCI Express

The Arria® 10 GX FPGA Development Kit is a high-performance platform for prototyping FPGA designs, featuring Arria 10 GX FPGA with high-speed transceivers and PCIe Gen3 support.

Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Data Science Development / Evaluation Kit DPU / IPU / AI NIC / SmartNIC Edge Machine Learning

The Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) is a high-speed signal integrity platform for PAM4 transceiver testing, featuring SMA and QSFP-DD connectivity and optimized layout for low-loss signal paths.

Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) (ES) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Data Science Development / Evaluation Kit DPU / IPU / AI NIC / SmartNIC Edge Machine Learning Public / On Premise Regional / District / Central Storage / Compression

The Agilex™ 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) (ES) is a high-speed signal integrity platform for PAM4 transceiver testing, featuring SMA and QSFP-DD connectivity and optimized layout for low-loss signal paths.

Agilex™ 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Development / Evaluation Kit Edge Machine Learning PCI Express Public / On Premise Storage / Compression

The Agilex™ 7 FPGA I-Series Development Kit is a high-performance platform for evaluating Agilex I-Series FPGAs, featuring PCIe Gen4 and QSFP-DD connectivity for advanced networking applications.

Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Data Science Development / Evaluation Kit DPU / IPU / AI NIC / SmartNIC Edge Machine Learning

The Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit is a signal integrity-focused platform for evaluating high-speed transceivers on Agilex I-Series FPGAs, featuring SMA connectors, MXMP and QSFP-DD ports for direct measurement.

Cyclone® V SX SoC Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit

The Cyclone® V SX SoC Development Kit offers a complete SoC FPGA platform with integrated ARM Cortex-A9 processors, ideal for embedded system development and hardware/software co-design.

Cyclone® V E FPGA Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit

The Cyclone® V E FPGA Development Kit offers a comprehensive general purpose development platform for Cyclone V FPGAs, and features an abundance of interactive options.

Cyclone® 10 LP FPGA Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit

The Cyclone® 10 LP Evaluation Kit is a low-cost, low-power platform ideal for entry-level FPGA development and education.

Cyclone® V GT FPGA Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit PCI Express

The Cyclone® V GT FPGA Development Kit provides a robust platform for evaluating high-speed transceiver capabilities of the Cyclone V GT FPGA, featuring PCIe Gen2 x4 and DDR3 support.

Arria® 10 SX SoC Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit

The Arria® 10 SX SoC Development Kit provides a comprehensive platform for developing advanced embedded, networking, and signal processing applications

Cyclone® 10 GX FPGA Development Kit Boards / SOMs / Dev Kits Development / Evaluation Kit PCI Express

The Cyclone® 10 GX Development Kit is a cost-effective platform for transceiver-based applications, featuring high-speed I/O and robust memory support.

Agilex™ 5 FPGA and SoC E-Series Development Kit (Premium) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Data Processing / Analysis / Acquisition Development / Evaluation Kit Edge Neural Network Public / On Premise

Agilex™ 5 FPGA and SoC E-Series Development Kit (Premium) delivers a complete prototyping and reference platform design environment that includes both hardware and software for your Agilex™ 5 FPGA E-Series development needs.

Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Artificial Intelligence (AI) Data Processing / Analysis / Acquisition Data Science Development / Evaluation Kit Edge Machine Learning Neural Network PCI Express Public / On Premise Regional / District / Central Storage / Compression

The Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023) offers a scalable platform for evaluating mid- to high-end Agilex FPGAs, featuring PCIe Gen4 and high-speed memory interfaces.

Agilex™ 5 FPGA and SoC E-Series Development Kit (Modular) Acceleration / AI / Cloud Boards / SOMs / Dev Kits Data Processing / Analysis / Acquisition Development / Evaluation Kit Edge Neural Network PCI Express Public / On Premise System-on-Module (SOM)

Agilex™ 5 FPGA and SoC E-Series Development Kit (Modular) delivers a complete prototyping and reference platform design environment that includes both hardware and software. It is a general-purpose evaluation board in PCIe form factor with HPS hardware features enabling you to develop industrial, video, and other embedded and edge applications.

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