Agilex 7 F-Tile Ethernet Hard IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The Agilex 7 FPGA F-Tile incorporates a fracturable, configurable, hardened Ethernet protocol stack for supporting rates from 10G to 400G, compatible with the IEEE 802.3 specification and other related Ethernet Consortium specifications. This intellectual property (IP) core implements Ethernet at data rates of 10 Gbps, 25 Gbps, 40 Gbps, 50 Gbps, 100 Gbps, 200 Gbps and 400 Gbps. It is available in multiple variants providing different combinations of Ethernet channels and features. These include optional Reed-Solomon Forward Error Correction (RSFEC) and optional IEEE 1588v2 Precision Time Protocol (PTP). The user can choose a media access control (MAC) and a physical coding sublayer (PCS) variation, a PCS-only variation, a Flexible Ethernet (FlexE) variation, or an Optical Transport Network (OTN) variation. This IP core is included in the IP library and is available from the IP Catalog.

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Key Features

The MAC provides cut-through frame processing to optimize latency and supports full wire line speed with a 64-byte frame length and back-to-back or mixed-length traffic with no dropped packets
All IP core variations are in full-duplex mode
The PHY supports: 1) 10GE-1, 25GE-1, 40GE-4, 50GE-1, 50GE-2, 100GE-1, 100GE-2, 100GE-4, 200GE-2, 200GE-4, 200GE-8, 400GE-4, and 400GE-8 modes. 2) Transceiver lanes operating at 10.3125 Gbps, 25.78125 Gbps, 26.5625 Gbps, 53.125 Gbps or 106.25 Gbps to support various Ethernet modes. 3) NRZ and PAM4 modes. 4) 64B/66B encoding with data striping and alignment markers to align data from multiple lanes. 5) Optional Reed-Solomon Forward Error Correction RS-FEC (528,514) usually termed KR-FEC or RS-FEC (544,514) usually termed KP-FEC. 6) Firecode FEC (CL74) support. 7) Auto-Negotiation (AN) as defined in IEEE Standard 802.3-2915 Clause 73 and the 25G Ethernet Consortium Schedule Draft 1.6. 8) Link Training (LT) as defined in IEEE Standard 802.3-2915 Clauses 92 and 93, and the 25G Ethernet Consortium Schedule Draft 1.6. 9) Optional deficit idle counter (DIC) options to maintain a finely controlled 8-byte, 10-byte, or 12-byte interpacket gap (IPG) minimum average, or allow the user to drive the IPG from the client interface. 10) Receiver (RX) skew variation tolerance that exceeds the IEEE 802.3-2015 High-Speed Ethernet Standard Clause 80.5 requirements
There is support for jumbo packets, RX CRC checking and error reporting, IEEE Standard 1588v2 Precision Time Protocol (PTP), Avalon Memory-Mapped (Avalon-MM) Management Interface, and dynamic reconfiguration between Ethernet rates

Offering Brief

Device Family	Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Encrypted Verilog