Design Gateway’s TOE1G-IP core provides a complete TCP Offload Engine (TOE) solution, implemented entirely in hardware for Altera FPGAs. This IP core enables high-throughput network communication by offloading the entire TCP/IP stack to the FPGA fabric. This eliminates the need for external processors or software-based protocol handling, making the TOE1G-IP ideal for real-time and high-performance systems such as remote data logging systems, industrial control systems, and defense applications where consistent and reliable data transfer is essential. The TOE1G-IP supports key TCP functions including connection setup and termination, retransmission control, and flow management—all handled autonomously in hardware. It features a user-friendly FIFO interface for data and a register-based control interface, ensuring seamless integration. Supporting both client and server roles, the core provides flexibility for a wide range of applications. Reference designs and e...
Design Gateway’s TOE1G-IP core provides a complete TCP Offload Engine (TOE) solution, implemented entirely in hardware for Altera FPGAs. This IP core enables high-throughput network communication by offloading the entire TCP/IP stack to the FPGA fabric. This eliminates the need for external processors or software-based protocol handling, making the TOE1G-IP ideal for real-time and high-performance systems such as remote data logging systems, industrial control systems, and defense applications where consistent and reliable data transfer is essential. The TOE1G-IP supports key TCP functions including connection setup and termination, retransmission control, and flow management—all handled autonomously in hardware. It features a user-friendly FIFO interface for data and a register-based control interface, ensuring seamless integration. Supporting both client and server roles, the core provides flexibility for a wide range of applications. Reference designs and evaluation files are available
Key Features
- All pure hardware TCP/IP protocol stack
- Support IPv4 protocol
- Supports Full Duplex communication
- Support both Server and Client mode (Passive/Active open and close)
- Support Jumbo frame
- 8-bit FIFO interface for data transfer
Offering Brief
Offering Brief
| Device Family | Arria® 10 SX SoC FPGA, Arria® 10 GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Cyclone® 10 GX FPGA |
|---|---|
| Offering Status | Production |
| Integrated Testbench | No |
| Evaluation License | Yes |
| Design Examples Available | Yes |
| Demo | Yes |
| Compliance | No |
| Latest Quartus Version Supported | 16.0.0 |
| Development Language | VHDL |
Reference Design
Ordering Information
NET-T1G-IP
from Direct
Documentation & Resources
Market Segment and Sub-Segments
Access
View Sub-Segments
Aerospace
View Sub-Segments
Consumer
View Sub-Segments.svg?h=0&itok=ZOeb-0LL)
Defense
View Sub-Segments
Government
View Sub-Segments
Medical
View Sub-SegmentsMedical
Imaging
Lab/Life Sciences
Non-Imaging Patient Devices
Other Medical
Ultrasound
Video
Test
View Sub-Segments
Transportation
View Sub-SegmentsTransportation
Automotive (Passenger Vehicles)
Non-Automotive Transportation
Transportation Infrastructure (non-charging)